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PDF ( 数据手册 , 数据表 ) STEL-2060CR

零件编号 STEL-2060CR
描述 45Mbps Viterbi Decoder
制造商 Intel
LOGO Intel LOGO 


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STEL-2060CR 数据手册, 描述, 功能
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STEL-2060C/CR
Data Sheet
STEL-2060C/CR
45 Mbps
Viterbi Decoder
R







STEL-2060CR pdf, 数据表
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must follow the rising edge of SYMCKIN by a minimum of
8 nsec. at this instant, otherwise the handover will not occur
correctly. This occurs once every 4 cycles of DCLKIN at rate
7/8, every 2 cycles at rate 3/4 and every 3 cycles at rate 2/3, the
number of cycles of SYMCKIN depending on whether the
parallel or sequential input mode is used, as well as the code
rate. Two examples of clock phasing for rate 3/4 parallel
operation are shown below.
SYMCKIN
Good
DCLKIN
Bad
In the first example the falling edges of DCLKIN never
coincide with the rising edges of SYMCKIN. Thus the timing
violation will never occur provided that the delay from the
non-coincident rising edges of SYMCKIN to the following
falling edge of DCLKIN (shown by the arrows) exceeds 8
nsec. In the second case the falling edge of DCLKIN coincides
with the rising edge of SYMCKIN once every two cycles of
DCLKIN, resulting in a 50% probability that this may be the
point at which the handover occurs, creating the problem
discussed above.
There are several ways to satisfy the timing requirement,
depending on the code rate. One effective way which works
at all rates is to generate SYMCKIN from DCLKIN by
puncturing the clock to reduce its frequency while keeping
all the edges synchronized; this will require the use of a small
FIFO to buffer the input symbols to cope with the punctured
clock. The rate 3/4 timing is shown below as an example.
SYMCKIN
DCLKIN
For rate 3/4 operation it is possible to generate the two clocks
with a mutual phase relationship that can exclude the timing
violation, as was shown in the first figure. As previously
stated, provided the two clocks can be generated as shown in
the first example, where only the rising edges of DCLKIN
coincide with the edges of SYMCKIN, the timing violation
will never occur provided that the delay from the non-
coincident rising edges of SYMCKIN to the following falling
edge of DCLKIN (shown by the arrows) exceeds 8 nsec. In
the example shown this will be true at data rates up to 30
Mbps. Care must be taken to ensure that jitter between the
clocks is kept low enough to avoid the timing violation
condition. A similar condition exists for rate 2/3 operation,
as shown below.
SYMCKIN
DCLKIN
Here, the timing is such that the falling edges of DCLKIN
only coincide with falling edges of SYMCKIN, never with
rising edges. In this case the timing violation never occurs at
any speed, since the non-coincident falling edges of DCLKIN
will trail the rising edges of SYMCKIN by approximately 8
nsec. at a speed of 45 Mbps. Again, the same caveat regarding
jitter must be observed. However, the symbol signal setup
and hold requirements, shown in page 11 of the data sheet
make it necessary for SYMCKIN to have a minimum low
time of 12 nsec. to satisfy these requirements, so that it is not
possible for this signal to be a square wave above 40 MHz for
this reason. Since the method for eliminating the clock
timing violation presented here relies on the use of square
waves (50% mark-space ratio), it cannot be used above 40
MHz because of the setup and hold time requirements.
Again, a similar condition exists for rate 7/8 operation, as
shown below.
SYMCKIN
DCLKIN
However, in this case the timing violation will begin to occur
at speeds over 15 Mbps, so that this method of solving the
timing problem is less useful for rate 7/8 operation.
Note that for sequential mode operation (PARL = 0) the
frequency of the SYMCKIN signal will be doubled in every
case. This presents a problem with the synchronized clock
method presented here since it will not be possible to generate
the necessary waveforms with the correct mutual phasing
guaranteed because of the phase ambiguity of the SYMCKIN
signal itself relative to the internal handover process. In this
case it will be necessary to use either the punctured clock
approach or the synchronized reset approach.
The third method, which, while having the disadvantage
that it is susceptible to loss of sync from disturbances, is
easier to implement than clock puncturing and provides a lot
more margin than simple clock phase synchronization. It
consists of a synchronized reset generator used in conjunction
with clock phase synchronization. This is shown below for
rate 7/8.
SYMCKIN
DCLKIN
RESET
Œ Ž ‘ ’“Œ
15 nsec. min.
This ensures that the STEL-2060CC starts up during the
optimum phase of the SYMCKIN/DCLKIN repetition cycle,
i.e., the phase with the maximum separation between the
rising edge of SYMCKIN and the next falling edge of DCLKIN;
STEL-2060C
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STEL-2060CR equivalent, schematic
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NODE SYNCHRONIZATION
In a communication system using Viterbi decoding the de-
coder will only operate correctly when the symbols G1 and
G2 are loaded into the decoder in the correct order. Identi-
fying which symbol is G1 and which one is G2 is referred to
as node synchronization. The STEL-2060C contains a circuit
designed to carry out the node synchronization function
automatically. It uses the internally generated metrics of the
received sequence to do this. These constantly changing
parameters are periodically renormalized to keep them
within bounds. If renormalization occurs too frequently it is
a good indication that the system is not converging, most
likely due to lack of node synchronization. The renormal-
ization rate at which the system will decide to change the
node sync is determined by the threshold parameter. This is
an 8-bit number which is set by the THR7-0 inputs. When the
renormalization count exceeds this value, the OOS output
will go high and the AUTO output will pulse high for one
clock cycle, as shown during Count Window N in the timing
diagram below. The counter is reset after a number of bits
determined by the number set by the COUNT7-0 inputs, so
that the threshold must be exceeded somewhere in that
period for resynchronization to take place. OOS will be
reset if the counter then counts through an entire window
and the threshold is not exceeded, as shown during Count
Window N + 1 in the timing diagram below. The most
suitable threshold setting will depend on the value of
Eb/N0, the coding rate, and the signal level at the G1 and G2
inputs. For full scale inputs, i.e., the peak signal values
almost saturate the digital inputs, suitable starting values
for the threshold will be 1% for Rate 1/2, 0.5% for Rates 2/3 to
6/7, and 0.1% for Rate 7/8. e.g., for Rate 1/2, if the number of
bits over which the measure is made is set to 512
(COUNT7-0 = 01H) the threshold should be set to 5. Setting
THR7-0 = 0 gives a value of 6, which is adequately close.
More reliable results will be obtained by counting over a
longer period to improve the averaging process, but this
increases the time taken to make a decision and hence to
acquire node sync. Thus, starting with a low count period
and then increasing it (and adjusting the threshold accord-
ingly to maintain a value of 1%) when OOS goes low will
result in a faster acquisition of correct node sync with a
lower probability of accidental loss of node sync once cor-
rect sync has been achieved. To use the internal node sync
the AUTO output must be connected to the SYNC input.
The synchronization sequence depends on the setting of the
PARL input. When PARL is set low it is assumed that the
data was modulated using BPSK, and when it is set high it is
NODE SYNC TIMING
Count Window N
ODCLK
AUTO
OOS
assumed that the data was modulated using QPSK. The
appropriate synchronization sequences will be invoked, as
shown in the node sync sequence tables. Note that the
pipeline delay through the device will be affected by the
node sync state. If multiple devices are used in parallel to
achieve higher data rates, it is necessary for the all devices to
have the same node sync state to equalize their pipeline
delays. It will be necessary to reset the devices together to
achieve this state
When internal depuncturing is used, additional node sync
states exist because of the uncertainty of the current symbol
position in the puncture sequence. In this case the node sync
circuit will also search through the sequence by adding
delays in the depuncturing process to precess through the
sequence. In the sequential input mode (PARL = 0) this is
simply an extension of the node sync process, since the
alternate state is achieved by delaying the symbols. In the
parallel input mode, however, this is different from the
"invert G2 and swap" process, and in this sync sequence
"invert G2 and swap" precedes the delay addition, so that
the system goes through both the initial and alternate states
for each delay addition tried. This is shown for the Rate
2/3 case. In each case the symbols are read into the depunc-
turing circuit in groups of three (in the BPSK mode) or six (in
the QPSK mode) and attempts are made to reinsert the
punctured symbol in all of the possible insertion positions.
The positions of the punctured symbols in the sequences are
shown by the asterisks (*). The resulting groups of four or
eight symbols are then decoded in pairs, resulting in two
decoded bits in the BPSK mode and four bits in the QPSK
mode. For higher rates the sequences will be extensions of
this procedure.
When external depuncturing is used, the determination of
which symbols were punctured, and need to be reinserted
into the symbol sequence, is part of the node sync process.
This is because the acquisition of correct node sync cannot be
completed until the punctured symbols are reinserted cor-
rectly. The AUTO and OOS outputs of the STEL-2060C can
be used as indicators of the operation of the internal node
sync process; OOS will remain high as long as node sync has
not been achieved and AUTO will pulse each time a new
node sync state is being tried. Since there are only two
possible internal node sync states, alternate pulses on the
AUTO output can be used as an indication that the depunc-
turing is incorrect and a new depuncturing sequence should
be tried externally.
Count Window N+1
STEL-2060C
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