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PDF ( 数据手册 , 数据表 ) MX10FMAXDQC

零件编号 MX10FMAXDQC
描述 SINGLE-CHIP 8-BIT MICROCONTROLLER
制造商 Macronix International
LOGO Macronix International LOGO 


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MX10FMAXDQC 数据手册, 描述, 功能
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FEATURE
• High performance CMOS MTP ROM CPU
• Operation Voltage 5V
• Up to 40MHz operation (3.5MHz to 40MHz)
• Three 16-bit timer/counters
• 256 Bytes of on-chip data RAM
• 64 Kbytes on-chip Flash memory
• 32 Programmable I/O lines
• 6 interrupt Sources
ADVANCED INFORMATION
MX10FMAXDQC
SINGLE-CHIP 8-BIT MICROCONTROLLER
• Code protection
• Two priority levels
• Power saving Idle and power down modes
• 64 K external program memory space
• 64 K external data memory space
• Four 8-bit I/O ports
• Full-duplex enhanced UART compatible with the stan-
dard 80C51 and the 80C52
GENERAL DESCRIPTION
The single-chip 8-bit microcontroller is manufactured in
MXIC's advanced CMOS process. This device uses the
same powerful instruction set, has the same architec-
ture, and is pin-to-pin compatible with the existing 80C51.
The added features make it an even more powerful
microcontroller for applications that require clock out-
put, and up/down counting capabilities such as motor
control. It also has a more versatile serial channel that
facilitates multi-processor communications.
PIN CONFIGURATIONS
44 PLCC
P1.5
P1.6
P1.7
RST
P3.0
N.C.
P3.1
P3.2
P3.3
P3.4
P3.5
6
7
12
17
18
1 44
MX10FMAXDQC
23
40
39 P0.4
P0.5
P0.6
P0.7
EA
34 N.C.
ALE
PSEN
P2.7
P2.6
29 P2.5
28
P/N:PM0626
REV. 0.1, DEC. 17, 1999
1







MX10FMAXDQC pdf, 数据表
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MX10FMAXDQC
5.1.2 Timing Waveform in Parallel Programming Mode
READ SIGNATURE AND NORMAL READ WAVEFORM
VDD
EA
ALE
ADDRESS
P3.3
A0=0 / A0=1
tAA
tCE
P2.7
P3.7
P3.1,P3.0
VDD
GND
P0.7-P0.0
tOE
000
tDF
Mft ID/Device ID
XXX
Read Signature
tDF
tAA
tCE
tOE
100
tDF
OUT
Normal Read
tAA tCE tOE tDF
Mim.
0
Max. 120 120 70
20
unit ns ns ns ns
P/N:PM0626
REV. 0.1, DEC 17, 1999
8







MX10FMAXDQC equivalent, schematic
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MX10FMAXDQC
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLs of ALE and Ports 1, 2 and 3. The
noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications
where capacitive loading exceeds 100 pF, the noise pulses on these signlas may exceed 0.8V. It may be desirable to qualify ALE or other
signals with a Schmitt Triggers, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the address lines are
stabilizing.
3. Minimum VCC for Power Down is 2V.
4. Typicals are based on a limited number of samples and are not guaranteed. The values listed are room temperature and 5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10mA
Maximum IOL per 8-bit port:
Port 0:
26mA
Ports 1, 2 and 3: 15mA
Maximum total IOL for all output pins:
71mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test
conditions.
VCC
VCC
VCC
P0
EA
ICC
VCC
RST
MX10FMAXDQC
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins disconnected
TCLCH = TCHCL = 5ns
Figure 6. ICC Test Condition, Active Mode
VCC
VCC
P0
ICC
VCC
EA
RST
MX10FMAXDQC
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins disconnected
TCLCH = TCHCL = 5ns
Figure 7. ICC Test Condition Idle Mode
P/N:PM0626
REV. 0.1, DEC 17, 1999
16










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