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PDF ( 数据手册 , 数据表 ) F321ARQTA

零件编号 F321ARQTA
描述 ST72F321
制造商 ST Microelectronics
LOGO ST Microelectronics LOGO 


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F321ARQTA 数据手册, 描述, 功能
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ST72321
64/44-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC,
FIVE TIMERS, SPI, SCI, I2C INTERFACE
Memories
– 32K to 60K dual voltage High Density Flash
(HDFlash) or ROM with read-out protection
capability. In-Application Programming and
In-Circuit Programming for HDFlash devices
– 1K to 2K RAM
– HDFlash endurance: 100 cycles, data reten-
tion: 20 years at 55°C
Clock, Reset And Supply Management
– Enhanced low voltage supervisor (LVD) for
main supply and auxiliary voltage detector
(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator os-
cillators, internal RC oscillator, clock security
system and bypass for external clock
– PLL for 2x frequency multiplication
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
Interrupt Management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– Top Level Interrupt (TLI) pin on 64-pin devices
– 15 external interrupt lines (on 4 vectors)
Up to 48 I/O Ports
– 48/32 multifunctional bidirectional I/O lines
– 34/22 alternate function lines
– 16/12 high sink outputs
5 Timers
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and pulse generator modes
– 8-bit PWM Auto-reload timer with: 2 input cap-
tures, 4 PWM outputs, output compare and
TQFP64
14 x 14
TQFP64
10 x 10
TQFP44
10 x 10
time base interrupt, external clock with event
detector
3 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
– I2C multimaster interface
1 Analog peripheral
– 10-bit ADC with up to 16 input ports
Instruction Set
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
Development Tools
– Full hardware/software development package
– In-Circuit Testing capability
Device Summary
Features
Program memory - bytes
RAM (stack) - bytes
Operating Voltage
Temp. Range
Package
ST72F321
(R/AR/J)9
Flash 60K
2048 (256)
ST72F321
(R/AR/J)7
ST72F321
(R/AR)6
ST72321
(R/AR/J)9
ST72321
(R/AR/J)7
Flash 48K
Flash 32K
ROM 60K
ROM 48K
1536 (256)
1024 (256)
2048 (256)
1536 (256)
3.8V to 5.5V
up to -40°C to +125°C
TQFP64 14x14 (R), TQFP64 10x10 (AR), TQFP44 10x10 (J)
ST72321
(R/AR)6
ROM 32K
1024 (256)
October 2004
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Rev. 1.10
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F321ARQTA pdf, 数据表
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ST72321
2 PIN DESCRIPTION
Figure 2. 64-Pin TQFP 14x14 and 10x10 Package Pinout
(HS) PE4
(HS) PE5
(HS) PE6
(HS) PE7
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / (HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4
45
ei0
5 44
6
7 ei2
43
42
8 41
9 40
10
11 ei3
39
38
12 37
13 36
14 35
15 ei1 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1
VDD_1
PA3 (HS)
PA2
PA1
PA0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
VSS_0
VDD_0
(HS) 20mA high sink capability
eix associated external interrupt vector
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F321ARQTA equivalent, schematic
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ST72321
Address
Block
Register
Label
Register Name
Reset
Status
Remarks
0058h
to
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Reserved Area (24 Bytes)
ADC
ADCCSR
ADCDRH
ADCDRL
Control/Status Register
Data High Register
Data Low Register
00h R/W
00h Read Only
00h Read Only
PWMDCR3 PWM AR Timer Duty Cycle Register 3
00h R/W
PWMDCR2 PWM AR Timer Duty Cycle Register 2
00h R/W
PWMDCR1 PWM AR Timer Duty Cycle Register 1
00h R/W
PWMDCR0 PWM AR Timer Duty Cycle Register 0
00h R/W
PWMCR
PWM AR Timer Control Register
00h R/W
PWM ART ARTCSR Auto-Reload Timer Control/Status Register
00h R/W
ARTCAR Auto-Reload Timer Counter Access Register 00h R/W
ARTARR Auto-Reload Timer Auto-Reload Register
00h R/W
ARTICCSR AR Timer Input Capture Control/Status Reg.
00h R/W
ARTICR1 AR Timer Input Capture Register 1
00h Read Only
ARTICR2 AR Timer Input Capture Register 1
00h Read Only
Reserved Area (2 Bytes)
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
tion, the values of the I/O pins are returned instead of the DR register contents.
2. The bits associated with unavailable pins must always keep their reset value.
16/189
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