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PDF ( 数据手册 , 数据表 ) LC0821-SFLYH6

零件编号 LC0821-SFLYH6
描述 LCD Module
制造商 ETC
LOGO ETC LOGO 


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LC0821-SFLYH6 数据手册, 描述, 功能
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LCD Module Specification
Model: LC0821-SFLYH6
Table of Contents
COVER & CONTENTS ······················· 1
BASIC SPECIFICATIONS ····················· 2
ABSOLUTE MAXIMUM RATINGS ················· 3
ELECTRICAL CHARACTERISTICS ··············· 4
OPERATING PRINCIPLES & METHODES ··········· 7
MPU INTERFACE ························· 12
DISPLAY CONTROL INSTRUCTIONS ············· 16
ELECTROOPTICAL CHARACTERISTICS ·········· 21
DIMENSIONAL OUTLINE ····················· 23
LCD MODULE NUMBERING SYSTEM ············· 24
PRECAUTIONS FOR USE OF LCD MODULE ········· 25







LC0821-SFLYH6 pdf, 数据表
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LC0821-SFLYH6
-8-
4.4 Display Data RAM (DD RAM)
The Display Data RAM (DD RAM) stores the display data represented in 8-bit character
codes. Its capacity is 80 x 8 bits or 80 characters. The Display Data RAM that is not used
for the display can be used as a general data RAM.
The DD RAM address (ADD) is set in the Address Counter (AC) and is represented in
hexadecimal. The address counter can be written by using the Set DD RAM Address
instruction and can be read by using the Read Busy Flag and Addressinstruction. In
each case, data bits DB0-DB6 represent the DD RAM address. In the read operation, bit
DB7 represents the Busy Flag.
MSB
LSB
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
Relations between DD RAM addresses and positions on the liquid crystal display are
shown below.
Display
1 2 3 --- 6 7 8 Position
DD Line 1 00H 01H 02H --- 05H 06H 07H
RAM
Addr. Line 2 40H 41H 42H --- 45H 46H 47H
When display shift operation is performed, the DD RAM address moves as follows:
For left shift:
Display
1 2 3 --- 6 7 8 Position
DD Line 1 01H 02H 03H --- 06H 07H 08H
RAM
Addr. Line 2 41H 42H 43H --- 46H 47H 48H
For right shift:
Display
1 2 3 --- 6 7 8 Position
DD Line 1 27H 00H 01H --- 04H 05H 06H
RAM
Addr. Line 2 67H 40H 41H --- 44H 45H 46H







LC0821-SFLYH6 equivalent, schematic
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LC0821-SFLYH6
- 16 -
6. DISPLAY CONTROL INSTRUCTIONS
Table 6.1 Instructions
Instruction code
Instruction
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Execution time
(fosc=270KHz)
Clear
Display
Return
Home
0
0
Entry Mode
Set
0
Display ON/
OFF Control
0
Cursor or
Display
Shift
0
Function Set 0
Set CGRAM
Address
Set DDRAM
Address
0
0
Read Busy
Flag and
Address
0
Write data
to CG or DD
RAM
Read data
from CG or
DD RAM
1
1
0
0
0
0
0
0
0
0
1
Clears entire display and sets
DDRAM address to 00H.
Sets DDRAM address to 00H in
0
0
0
0
0
0
0
1
-
AC and returns shifted display to
its original position. The contents
of DDRAM remain unchanged.
Sets cursor move direction and
0
0
0
0
0
0
1
I/D
SH
enable the shift of entire display.
These operations are performed
during data write and read.
Set ON/OFF of entire display
0
0
0
0
0
1
D
C
B
(D), cursor ON/OFF(C), and
blinking of cursor position
character(B).
000
0 1 S/C R/L -
Moves cursor and shifts display
- without changing DDRAM
contents.
Sets interface data length (DL:
000
1 DL N F
-
-
8-bit/4-bit), numbers of display
line (N: 2-line/1-line), and display
font type (F: 5x11dots/5x8dots)
0
0
1
AC5
AC4
AC3
AC2
AC1
AC0
Set CGRAM
counter.
address
in
address
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Set DDRAM
Counter.
address
in
address
Reads busy flag (BF) indicating
internal operation is being
1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 performed and reads address
counter contents.
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data into internal RAM
(DDRAM/CGRAM).
Read data from internal RAM
1 D7 D6 D5 D4 D3 D2 D1 D0 (DDRAM/CGRAM).
1.53ms
1.53ms
39μs
39μs
39μs
39μs
39μs
39μs
0μs
43us
43us
-: dont care
Note: 1. Make sure to check the busy flag before sending the instruction to the display. If
the busy flag is not checked, the time between first and next instruction must be
longer than the instruction execution time list in the Table 6.1.
2. After execution of CG RAM/DD RAM data write or read instruction, the RAM
address counter is increased or decreased by 1. The RAM address counter is
updated after the busy flag turns off.










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