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PDF ( 数据手册 , 数据表 ) D8189

零件编号 D8189
描述 AD8189
制造商 Analog Devices
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D8189 数据手册, 描述, 功能
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FEATURES
Fully buffered inputs and outputs
Fast channel-to-channel switching: 4 ns
Single-supply operation (5 V)
High speed
350 MHz bandwidth (−3 dB) @ 200 mV p-p
300 MHz bandwidth (−3 dB) @ 2 V p-p
Slew rate: 1000 V/μs
Fast settling time: 7 ns to 0.1%
Low current: 19 mA/20 mA
Excellent video specifications: load resistor (RL) = 150 Ω
Differential gain error: 0.05%
Differential phase error: 0.05°
Low glitch
All hostile crosstalk
−84 dB @ 5 MHz
−52 dB @ 100 MHz
High off isolation: −95 dB @ 5 MHz
Low cost
Fast, high impedance disable feature for connecting
multiple outputs
Logic-shifted outputs
APPLICATIONS
Switching RGB in LCD and plasma displays
RGB video switchers and routers
GENERAL DESCRIPTION
The AD8188 (G = 1) and AD8189 (G = 2) are high speed,
single-supply, triple 2-to-1 multiplexers. They offer −3 dB small
signal bandwidth of 350 MHz and −3 dB large signal bandwidth
of 300 MHz, along with a slew rate in excess of 1000 V/μs. With
−84 dB of all hostile crosstalk and −95 dB off isolation, the parts
are well suited for many high speed applications. The
differential gain and differential phase error of 0.05% and 0.05°
respectively, along with 0.1 dB flatness to 70 MHz, make the
AD8188 and AD8189 ideal for professional and component
video multiplexing. The parts offer 4 ns switching time, making
them an excellent choice for switching video signals, while
consuming less than 20 mA on a single 5 V supply (100 mW).
Both devices have a high speed disable feature that sets the
outputs into a high impedance state. This allows the building of
larger input arrays while minimizing off-channel output
loading. The devices are offered in a 24-lead TSSOP.
350 MHz Single-Supply (5 V)
Triple 2:1 Multiplexers
AD8188/AD8189
FUNCTIONAL BLOCK DIAGRAM
IN0A 1
DGND 2
IN1A 3
VREF 4
IN2A 5
VCC
VEE
IN2B
6
7
8
VEE 9
IN1B 10
VEE 11
IN0B 12
LOGIC
24 VCC
23 OE
SELECT
ENABLE
0
22 SEL A/B
21 VCC
20 OUT0
19 VEE
1 18 OUT1
17 VCC
2 16 OUT2
AD8188/AD8189
15 VEE
14 DVCC
13 VCC
Figure 1.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
0
6.0
5.5
5.0
INPUT
4.5
4.0
3.5
3.0
OUTPUT
2.5
2.0
1.5
1.0
5 10 15 20 25
TIME (ns)
Figure 2. AD8189 Video Amplitude Pulse Response,
VOUT = 1.4 V p-p, RL = 150 Ω
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.







D8189 pdf, 数据表
AD8188/AD8189
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.1
1 10 100
FREQUENCY (MHz)
Figure 11. AD8188 All Hostile Crosstalk vs. Frequency
(Drive All INxA, Listen to Output with INxB Selected)
1k
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.1
1 10 100
FREQUENCY (MHz)
1k
Figure 12. AD8188 Adjacent Channel Crosstalk vs. Frequency
(Drive One INxA, Listen to an Adjacent Output with INxB Selected)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
10 100
FREQUENCY (MHz)
Figure 13. AD8188 Off Isolation vs. Frequency
(Drive Inputs with OE Tied Low)
1k
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.1
1 10 100
FREQUENCY (MHz)
Figure 14. AD8189 All Hostile Crosstalk vs. Frequency
(Drive All INxA, Listen to Output with INxB Selected)
1k
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.1
1 10 100
FREQUENCY (MHz)
1k
Figure 15. AD8189 Adjacent Channel Crosstalk vs. Frequency
(Drive One INxA, Listen to an Adjacent Output with INxB Selected)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
1
10 100
FREQUENCY (MHz)
Figure 16. AD8189 Off Isolation vs. Frequency
(Drive Inputs with OE Tied Low)
1k
Rev. 0 | Page 8 of 24







D8189 equivalent, schematic
AD8188/AD8189
5V
10k
10k
VREF
1µF
CAP MUST BE LARGE
ENOUGH TO ABSORB
TRANSIENT CURRENTS
WITH MINIMUM BOUNCE.
Figure 49. Alternate Method for Synthesis of a False Ground Reference
AC-COUPLED INPUTS
Using ac-coupled inputs presents an interesting challenge for
video systems operating from a single 5 V supply. In NTSC and
PAL video systems, 700 mV is the approximate difference
between the maximum signal voltage and black level. It is
assumed that sync has been stripped. However, given the two
pathological cases shown in Figure 50, a dynamic range of twice
the maximum signal swing is required if the inputs are to be
ac-coupled. A possible solution is to use a dc restore circuit
before the mux.
WHITE LINE WITH BLACK PIXEL
+700mV
VREF
VAVG
VAVG
BLACK LINE WITH WHITE PIXEL
VREF
–700mV
+5V
VSIGNAL
GND
VINPUT = VREF + VSIGNAL
VREF ~ VAVG
VREF IS A DC VOLTAGE
SET BY THE RESISTORS
Figure 50. Pathological Case for Input Dynamic Range
TOLERANCE TO CAPACITIVE LOAD
Op amps are sensitive to reactive loads. A capacitive load at the
output appears in parallel with an effective resistance (REFF) of
REFF = (RL || rO)
where RL is the discrete resistive load, and rO is the open loop
output impedance, approximately 15 Ω for these muxes.
The load pole (fLOAD) at
f LOAD
=
2π
1
REFF
CL
can seriously degrade phase margin and, therefore, stability. The
old workaround is to place a small series resistor directly at the
output to isolate the load pole. While effective, this ruse also
affects the dc and termination characteristics of a 75 Ω system.
The AD8188 and AD8189 are built with a variable compensation
scheme that senses the output reactance and trades bandwidth
for phase margin, ensuring faster settling and lower overshoot
at higher capacitive loads.
SECONDARY SUPPLIES AND SUPPLY BYPASSING
The high current output transistors are given their own supply
pins (Pin 15, Pin 17, Pin 19, and Pin 21) to reduce supply noise
on-chip and to improve output isolation. Because these
secondary, high current supply pins are not connected on-chip
to the primary analog supplies, VCC/VEE (Pin 6, Pin 7, Pin 9,
Pin 11, Pin 13, and Pin 24), some care should be taken to ensure
that the supply bypass capacitors are connected to the correct
pins. At a minimum, the primary supplies should be bypassed.
Pin 6 and Pin 7 can be a convenient place to accomplish this.
Stacked power and ground planes are a convenient way to
bypass the high current supply pins (see Figure 51).
IN0A 1
24 VCC
DGND 2
23 OE
IN1A 3
22 SEL A/B
VREF 4
21 VCC
IN2A 5
20 OUT0
VCC 6
0.1µF 1µF
VEE 7
MUX1
19 VEE
18 OUT1
IN2B 8
MUX2
17 VCC
VEE 9
16 OUT2
IN1B 10
MUX3
15 VEE
VEE 11
14 DVCC
IN0B 12
13 VCC
Figure 51. Detail of Primary and Secondary Supplies
SPLIT-SUPPLY OPERATION
Operating from split supplies (for example, [+3 V/−2 V] or
±2.5 V) simplifies the selection of the VREF voltage and load
resistor termination voltage. In this case, it is convenient to tie
VREF to ground. The logic inputs are internally level-shifted to
allow the digital supplies and logic inputs to operate from 0 V
and 5 V when powering the analog circuits from split supplies.
The maximum voltage difference between DVCC and VEE must
not exceed 8 V (see Figure 52).
DIGITAL SUPPLIES
(+5V)
DVCC
ANALOG SUPPLIES
(+2.5V)
VCC
8V MAX
(0V)
DGND
(–2.5V)
VEE
Figure 52. Split-Supply Operation
Rev. 0 | Page 16 of 24










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