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PDF ( 数据手册 , 数据表 ) 92HD71B5

零件编号 92HD71B5
描述 4-CHANNEL HD AUDIO CODEC OPTIMIZED
制造商 IDT
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92HD71B5 数据手册, 描述, 功能
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4-CHANNEL HD AUDIO CODECS OPTIMIZED
FOR LOW POWER
92HD71B5
Description
The 92HD71B5 codec is a low power optimized, high
fidelity, 4-channel audio codec compatible with Intel’s High
Definition (HD) Audio Interface. The 92HD71B5 codec
provides stereo 24-bit resolution with sample rates up to
192kHz. Dual SPDIF provides connectivity to consumer
electronic equipment that is WLP complaint. The
92HD71B5 provides high quality, HD Audio capability to
notebook and business desktop PC applications.
Features
• 4 Channels (2 stereo DACs and 2 stereo ADCs) with
24-bit resolution
• Supports full-duplex stereo audio and simultaneous VoIP
• Provides a mono output for laptop sub-woofer
• Microsoft WLP 3/4 premium logo compliant, as
defined in WLP 3.09
• Optimized and flexible power management with
pop/click mitigation
• 2 independent S/PDIF Output converters for WLP
compliant HDMI/SPDIF support.
• Support for 1.5V and 3.3V HDA signaling with
runtime selection
• Digital microphone input (mono, stereo, or quad
array)
• 2 Adjustable VREF Out pins for microphone bias
• 4 analog ports
• Supports to 2 stereo microphone inputs
• Two-pin volume up/down control
• Digital PC Beep to all outputs
• Integrated headphone amp
• Jack insertion detection
• Sample rates up to 192kHz
• +3.3 V, +4 V, +4.75 V and +5 V analog power supply
options
• 48-pin QFP and 48-pad QFN RoHS packages
Preliminary Datasheet
Block Diagram
X
DUAL SPDIF
Port A
Port B
Port C
Port D
SPDIF Out 1
SPDIF Out 2
IDT™ CONFIDENTIAL AND PROPRIETARY
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
1
92HD71B5
V 0.9 09/07







92HD71B5 pdf, 数据表
92HD71B5
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
PC AUDIO
13. REVISION HISTORY ........................................................................................................... 192
LIST OF FIGURES
Figure 1. 92HD71B5 Block Diagram ..............................................................................................................10
Figure 2. System Diagram ............................................................................................................................10
Figure 3. Multi-channel capture ......................................................................................................................16
Figure 4. Multi-channel timing diagram ..........................................................................................................16
Figure 5. Single Digital Microphone (data is ported to both left and right channels .......................................18
Figure 6. Stereo Digital Microphone Configuration ........................................................................................19
Figure 7. Quad Digital Microphone Configuration ..........................................................................................20
Figure 8. Volume Knob ..................................................................................................................................23
Figure 9. Port Configurations .........................................................................................................................30
Figure 10. 92HD71B5 Functional Block Diagram ..........................................................................................31
Figure 11. 92HD71B5 Widget Diagram ..........................................................................................................32
Figure 12. Pin Assignment ...........................................................................................................................185
Figure 13. 48-pad QFN Package Drawing ...................................................................................................188
Figure 14. 48-pin QFP Package Drawing ....................................................................................................189
Figure 15. Solder Reflow Profile .................................................................................................................190
LIST OF TABLES
Figure 1. 92HD71B5 Block Diagram ..............................................................................................................10
Figure 2. System Diagram ............................................................................................................................10
Figure 3. Multi-channel capture ......................................................................................................................16
Figure 4. Multi-channel timing diagram ..........................................................................................................16
Figure 5. Single Digital Microphone (data is ported to both left and right channels .......................................18
Figure 6. Stereo Digital Microphone Configuration ........................................................................................19
Figure 7. Quad Digital Microphone Configuration ..........................................................................................20
Figure 8. Volume Knob ..................................................................................................................................23
Figure 9. Port Configurations .........................................................................................................................30
Figure 10. 92HD71B5 Functional Block Diagram ..........................................................................................31
Figure 11. 92HD71B5 Widget Diagram ..........................................................................................................32
Figure 12. Pin Assignment ...........................................................................................................................185
Figure 13. 48-pad QFN Package Drawing ...................................................................................................188
Figure 14. 48-pin QFP Package Drawing ....................................................................................................189
Figure 15. Solder Reflow Profile .................................................................................................................190
IDT™ CONFIDENTIAL AND PROPRIETARY
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
8
92HD71B5
V 0.9 09/07







92HD71B5 equivalent, schematic
92HD71B5
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
PC AUDIO
ADC0.CnvrtID.Channel = 0
ADC1.CnvrtID.Channel = 2
ADC0.CnvrtID.Channel = 2
ADC1.CnvrtID.Channel = 0
Stream ID
Stream ID
Figure 3. Multi-channel capture
Data
Length
ADC0
Left Channel
ADC0
Right Channel
Data
Length
ADC1
Left Channel
ADC1
Right Channel
ADC1
Left Channel
ADC0
Left Channel
ADC1
Right Channel
Null PAD
ADC0
Right Channel
Null PAD
BITCLK
The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1.
Figure 4. Multi-channel timing diagram
SDI
0
0
0
1
0
0
1
1
0
0
ADC0
L23
ADC0
L0
ADC0
R23
ADC0
R0
ADC1
L23
ADC1
L0
ADC1
R23
ADC1
R0
STREAM ID
DATA LENGTH
STREAM TAG
LEFT
RIGHT
LEFT
RIGHT
ADC0
ADC1
DATA BLOCK
1.4.11.
EAPD
The EAPD pin (pin 47) also supports SPDIF and GPIO functions. The pin defaults to EAPD after
power on reset and will remain in EAPD mode until either GPIO is enabled for pin 47 or the port I/O
is enabled to support SPDIF. The EAPD value is reflected on the EAPD pin; a 1 causes the external
amplifier to power up, and a 0 causes it to power down. When the EAPD value = 1, the EAPD pin
must be placed in a state appropriate to the current power state of the associated Pin Widget even
though the EAPD value may remain 1. The default state of this pin is 0 (driving low) and a Pull-down
prevents the line from floating high when the part is in reset.
AFG Power
State
D0-D3
RESET#
Asserted (Low)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
Table 7. EAPD Behavior
GPIO Enable
-
Enabled
Disabled
Disabled
Disabled
Output Enable
-
-
Enabled
Disabled
Disabled
EAPD Power
State
-
-
-
D2-D3
D0-D1
Pin Behavior
Hi-Z (internal pull-down enabled)
immediately after power on,
otherwise the previous state is
retained until the rising edge of
RESET#
Active - Pin reflects GPIO0
configuration (internal pull-up
enabled)
Active - Pin Drives SPDIFOut0/1
output (internal pull-down enabled)
Hi-Z (internal pull-down enabled)
Active - Pin drives the value of the
EAPD bit (internal pull-down
enabled)
IDT™ CONFIDENTIAL AND PROPRIETARY
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
16
92HD71B5
V 0.9 09/07










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