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PDF ( 数据手册 , 数据表 ) AZ100E131

零件编号 AZ100E131
描述 ECL/PECL 4-bit D Flip-Flop
制造商 Arizona Microtek
LOGO Arizona Microtek LOGO 


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AZ100E131 数据手册, 描述, 功能
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ARIZONA MICROTEK, INC.
AZ10E131
AZ100E131
ECL/PECL 4-bit D Flip-Flop
FEATURES
PACKAGE AVAILABILITY
1100 MHz Min. Toggle Frequency
Differential Outputs
PACKAGE PART NUMBER MARKING NOTES
Individual and Common Clocks
Individual Resets (asynchronous)
Paired Sets (asynchronous)
Operating Range of 4.2V to 5.46V
PLCC 28
AZ10E131FN
AZM10E131
<Date Code>
1,2
PLCC 28
AZ100E131FN
AZM100E131
<Date Code>
1,2
1 Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
75kΩ Internal Input Pulldown Resistors 2 Date code format: “YY” for year followed by “WW” for week.
Direct Replacement for On Semiconductor
MC10E131 & MC100E131
DESCRIPTION
The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be
clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (C¯¯En) inputs for clocking.
Common clocking is achieved by holding the C¯¯En inputs LOW and using CC to clock all four flip-flops. In this
case, the C¯¯En inputs perform the function of controlling the common clock to each flip-flop.
Individual asynchronous resets are provided (Rn). Asynchronous set controls (Sn) are ganged together in pairs,
with the pairing chosen to reflect physical chip symmetry.
Data enters the master when both CC and C¯¯En are LOW, and transfers to the slave when either CC or C¯¯En (or
both) go HIGH.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
CE3
D3
R3
25
26
27
D2 CE2 R2 VCCO Q3
24
23 22
21
20
Q3
19
18
17
Q2
Q2
S12 28
VEE
CC
S03
1
2
3
Pinout: 28-Lead
PLCC (top view)
16 VCC
15 Q1
14 Q1
13 Q0
D0 4
12 Q0
5 6 7 8 9 10 11
CE0
R0
D1 CE1
R1
NC VCCO
* All VCC and VCCO pins are tied together on the die.
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com












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