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PDF ( 数据手册 , 数据表 ) AD5024

零件编号 AD5024
描述 (AD50x4) DAC SPI Interface
制造商 Analog Devices
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AD5024 数据手册, 描述, 功能
Data Sheet
Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad,
SPI Interface, 4.5 V to 5.5 V in TSSOP
AD5024/AD5044/AD5064
FEATURES
Low power quad 12-/14-/16-bit DAC, ±1 LSB INL
Pin compatible and performance upgrade to AD5666
Individual and common voltage reference pin options
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
3 power-down functions and per-channel power-down
Hardware LDAC with software LDAC override function
CLR function to programmable code
SDO daisy-chaining option
14-/16-lead TSSOP
Internal reference buffer and internal output amplifier
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAMS
VDD
VREFIN
AD5064-1
SCLK
SYNC
DIN
SDO
LDAC
INTERFACE
LOGIC AND
SHIFT
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
POWER-ON
RESET
DAC
REGISTER
DAC A
DAC B
DAC C
DAC D
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
VOUTD
POWER-DOWN
LOGIC
LDAC CLR
POR
GND
Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666
AD5024/
AD5044/
AD5064 LDAC
SCLK
SYNC
DIN
INTERFACE
LOGIC AND
SHIFT
REGISTER
VDD
VREFA VREFB
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
POWER-ON
RESET
DAC
REGISTER
DAC A
DAC B
DAC C
DAC D
BUFFER
BUFFER
BUFFER
BUFFER
POWER-DOWN
LOGIC
VOUTA
VOUTB
VOUTC
VOUTD
LDAC CLR
POR
VREFC VREFD
GND
Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins
GENERAL DESCRIPTION
The AD5024/AD5044/AD5064/AD5064-1 are low power, quad
12-/14-/16-bit buffered voltage output nanoDAC® converters
that offer relative accuracy specifications of 1 LSB INL and 1 LSB
DNL with the AD5024/AD5044/AD5064 individual reference
pin and the AD5064-1 common reference pin options. The
AD5024/AD5044/AD5064/AD5064-1 can operate from a single
4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1
also offer a differential accuracy specification of ±1 LSB. The
parts use a versatile 3-wire, low power Schmitt trigger serial
interface that operates at clock rates up to 50 MHz and is compati-
ble with standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. Integrated reference buffers and output amplifiers are
also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1
incorporate a power-on reset circuit that ensures the DAC
output powers up to zero scale or midscale and remains there
until a valid write takes place to the device. The AD5024/AD5044/
AD5064/AD5064-1 contain a power-down feature that reduces
the current consumption of the device to typically 400 nA at 5 V
and provides software selectable output loads while in power-
down mode. Total unadjusted error for the parts is <2 mV.
PRODUCT HIGHLIGHTS
1. Quad channel available in 14-/16-lead TSSOP packages.
2. 16-bit accurate, 1 LSB INL.
3. High speed serial interface with clock speeds up to 50 MHz.
4. Reset to known output voltage (zero scale or midscale).
Table 1. Related Devices
Part No.
AD5666
AD5025/AD5045/AD5065
AD5062, AD5063
AD5061
AD5040/AD5060
Description
Quad,16-bit buffered DAC,
16 LSB INL, TSSOP
Dual, 16-bit buffered DACs,
1 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL, SOT-23,
MSOP
16-bit nanoDAC, 4 LSB INL, SOT-23
14-/16-bit nanoDAC, 1 LSB INL,
SOT-23
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







AD5024 pdf, 数据表
AD5024/AD5044/AD5064
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
LDAC 1
SYNC 2
VDD
VOUTA
VOUTC
3
4
5
POR 6
VREFIN 7
AD5064-1
TOP VIEW
(Not to Scale)
14 SCLK
13 DIN
12 GND
11 VOUTB
10 VOUTD
9 CLR
8 SDO
Figure 6. 14-Lead TSSOP (RU-14)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 LDAC
LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing
this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows
all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode.
When daisy-chain mode is enabled, this pin cannot be tied permanently low; the LDAC pin should be
used in asynchronous LDAC update mode, as shown in Figure 5, and the LDAC pin must be brought
high after pulsing.
2 SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the device.
3 VDD
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4 VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5 VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
6 POR
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to VDD
powers up all four DACs to midscale.
7 VREFIN
8 SDO
This is a common pin for reference input for DAC A, DAC B, DAC C, and DAC D.
Serial Data Output. Can be used to daisy-chain a number of AD5064-1 devices together. The serial data
is transferred on the rising edge of SCLK and is valid on the falling edge of the clock.
9 CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
10 VOUTD
11 VOUTB
12 GND
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
13 DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the
falling edge of the serial clock input.
14 SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz.
Rev. F | Page 8 of 28







AD5024 equivalent, schematic
AD5024/AD5044/AD5064
VDD = 5V,VREF = 4.096V
TA = 25°C
DAC A 129mV p-p
TA = 25°C
VDD = 5V, VREF = 4.096V
Data Sheet
DAC A 170mV p-p
SCLK
CH1 20mV CH2 5V
M4µs
T 8.6%
A CH2 1.2V
Figure 44. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale,
No Load
SCLK
CH1 20mV CH2 5V
M4µs
T 8.6%
A CH2 1.2V
Figure 45. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale,
5 kΩ/200 pF Load
Rev. F | Page 16 of 28










页数 28 页
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