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PDF ( 数据手册 , 数据表 ) 33975A

零件编号 33975A
描述 Multiple Switch Detection Interface
制造商 Freescale Semiconductor
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33975A 数据手册, 描述, 功能
www.DFaretaeSshceeatl4eUS.ceommiconductor
Technical Data
Document order number: MC33975
Rev 4.0, 08/2005
Multiple Switch Detection
Interface with Suppressed
Wake-Up and 32mA Wetting
Current
Freescale offers multiple Switch Detection Interface Devices. The
33975 Multiple Switch Detection Interface with Suppressed Wake-Up
is designed to detect the closing and opening of up to 22 switch
contacts. The switch status, either open or closed, is transferred to the
microprocessor unit (MCU) through a serial peripheral interface (SPI).
The device also features a 22-to-1 analog multiplexer for reading
inputs as analog.
33975
33975A
MULTIPLE SWITCH
DETECTION INTERFACE WITH
SUPPRESSED WAKE-UP
The 33975 device has two modes of operation, Normal and Sleep.
Normal mode allows programming of the device and supplies switch
contacts with pull-up or pull-down current as it monitors switch change
of state. The Sleep mode provides low quiescent current, which makes
the 33975 ideal for automotive and industrial products requiring low
sleep state currents.
Improvements are a programmable interrupt timer for Sleep mode
that can be disabled, switch detection currents of 32 mA and 4.0 mA
for switch-to-ground inputs, and an interrupt bit that can be reset.
EK Suffix (Pb-Free)
98ARL10543D
32-TERMINAL SOICW EP
Features
ORDERING INFORMATION
• Designed to Operate 5.5 V VPWR 28 V
• Switch Input Voltage Range -14 V to VPWR
• Interfaces Directly to Microprocessor Using 3.3 V/5.0 V SPI
Protocol
• Selectable Wake-Up on Change of State
Device
MC33975EK/R2
PC33975AEK/R2
Temperature
Range (TA)
-40°C to 125°C
Package
32 SOICW-EP
• Selectable Wetting Current (32 mA or 4.0 mA for switch-to-ground
inputs)
• 8 Programmable Inputs (Switches to Battery or Ground)
• 14 Switch-to-Ground Inputs
• VPWR Standby Current 100 µA Typical, VDD Standby Current 20 µA Typical
• Pb-free 32-terminal suffix EK
VDD
VBAT
VBAT
VBAT
33975
SP0 VPWR
SP1
VDD
SP7
SG0
SG1
SG12
WAKE
SI
SCLK
CS
SO
INT
AMUX
VDD
Power Supply
LVI
Enable
Watchdog
Reset
MCU
MOSI
SCLK
CS
MISO
INT
AN0
SG13
GND
Figure 1. 33975 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.







33975A pdf, 数据表
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions of 3.0 V VDD 5.5 V, 8.0 V VPWR 28V, -40°C TC 125°C unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max Unit
DIGITAL INTERFACE
Input Logic High-Voltage Thresholds (10)
Input Logic Low-Voltage Thresholds (10)
SCLK, SI, Tri-State SO Input Current
0.0 V to VDD
CS Input Current
CS = VDD
CS Pull-Up Current
CS = 0.0 V
SO High-State Output Voltage
ISO(high) = -200 µA
SO Low-State Output Voltage
ISO(high) = 1.6 mA
Input Capacitance on SCLK, SI, Tri-State SO (11)
INT Internal Pull-Up Current
INT Voltage
INT = Open Circuit
INT Voltage
IINT = 1.0 mA
WAKE Internal Pull-Up Current
WAKE Voltage
WAKE = Open Circuit
WAKE Voltage
IWAKE = 1.0 mA
WAKE Voltage (11)
Maximum Voltage Applied to WAKE Through External Pull-Up
VIH
0.7 x VDD
VDD + 0.3
V
VIL
GND - 0.3
0.2 x VDD
V
ISCLK, ISI,
µA
ISO(Tri)
-10
10
ICS µA
-10 – 10
ICS
VSO(high)
VSO(low)
30
VDD - 0.8
100
VDD
0.4
µA
V
V
CIN
V INT (high)
V INT (low)
15
VDD - 0.5
40
0.2
20
100
VDD
0.4
pF
µA
V
V
I WAKE (pu)
20
40 100 µA
V WAKE (high)
V
4.0 4.3 5.3
V WAKE(low)
V
0.2 0.4
V WAKE(max)
V
– 40
Notes
10. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK.
11. This parameter is guaranteed by design however, is not production tested.
33975
8
Analog Integrated Circuit Device Data
Freescale Semiconductor







33975A equivalent, schematic
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 9. Wetting Current Timer Enable Command
Wetting Current Timer Commands
Command Bits
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 1 X X X X X X X X sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
0 0 0 0 1 0 0 0 X X sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3210
TRI-STATE REGISTER
The tri-state command is use to set the SPn or SGn input
node as high impedance (refer to Table 10). By setting the
Tri-State Register bit to logic [1], the input will be high
impedance regardless of the metallic command setting. The
Table 10. Tri-State Command
comparator on each input remains active. This command
allows the use of each input as a comparator with a 4.0 V
threshold. The MCU may change or update the Tri-State
Register via software at any time in Normal mode.
Tri-State Commands
Command Bits
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 1 X X X X X X X X sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
0 0 0 0 1 0 1 0 X X sg13 sg12 sg11 sg10 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
33975
16
Analog Integrated Circuit Device Data
Freescale Semiconductor










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