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PDF ( 数据手册 , 数据表 ) 74LVQ161

零件编号 74LVQ161
描述 SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
制造商 STMicroelectronics
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74LVQ161 数据手册, 描述, 功能
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74LVQ161
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
s HIGH SPEED:
fMAX = 180 MHz (TYP.) at VCC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V
s 75TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 161
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ161 is a low voltage CMOS
SYNCHRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology. It is
ideal for low power and low noise 3.3V
applications. It is a 4 bit binary counter with
Asynchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ161MTR
74LVQ161TTR
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (PE) and Count Enable Carry Input
(TE), determine the mode of operation as shown
in the Truth Table. A LOW signal on CLEAR
overrides counting and parallel loading and sets
all outputs on LOW state. A LOW signal on LOAD
overrides counting and allows information on
Parallel Data Qn inputs to be loaded into the
flip-flops on the next rising edge of CLOCK. With
LOAD and CLEAR, PE and TE permit counting
when both are high. Conversely, a LOW signal on
either PE and TE inhibits counting. All inputs and
outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 2
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74LVQ161 pdf, 数据表
74LVQ161
Figure 9: Waveform - Propagation Delays Countable Mode (f=1MHz; 50% duty cycle)
Figure 10: Waveform - Propagation Delays Cascade Mode (f=1MHz; 50% duty cycle)
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