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PDF ( 数据手册 , 数据表 ) NH82801HR

零件编号 NH82801HR
描述 I/O Controller Hub 8
制造商 Intel
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NH82801HR 数据手册, 描述, 功能
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Intel® I/O Controller Hub 8 (ICH8)
Family
Datasheet
– For the Intel® 82801HB ICH8 and 82801HR ICH8R I/O Controller
Hubs
June 2006
Document Number: 313056-001







NH82801HR pdf, 数据表
Contents
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5.18
5.19
5.17.3 Data Encoding and Bit Stuffing............................................................................ 173
5.17.4 Bus Protocol ........................................................................................................ 173
5.17.4.1 Bit Ordering.......................................................................................... 173
5.17.4.2 SYNC Field .......................................................................................... 173
5.17.4.3 Packet Field Formats ........................................................................... 174
5.17.4.4 Address Fields ..................................................................................... 174
5.17.4.5 Frame Number Field ............................................................................ 174
5.17.4.6 Data Field............................................................................................. 174
5.17.4.7 Cyclic Redundancy Check (CRC)........................................................ 174
5.17.5 Packet Formats.................................................................................................... 174
5.17.6 USB Interrupts ..................................................................................................... 174
5.17.6.1 Transaction-Based Interrupts............................................................... 174
5.17.6.2 Non-Transaction Based Interrupts ....................................................... 177
5.17.7 USB Power Management .................................................................................... 177
5.17.8 USB Legacy Keyboard Operation........................................................................ 178
USB EHCI Host Controllers (D29:F7 and D26:F7) ........................................................... 180
5.18.1 EHC Initialization ................................................................................................. 180
5.18.1.1 BIOS Initialization................................................................................. 180
5.18.1.2 Driver Initialization................................................................................ 180
5.18.1.3 EHC Resets ......................................................................................... 181
5.18.2 Data Structures in Main Memory ......................................................................... 181
5.18.3 USB 2.0 Enhanced Host Controller DMA ............................................................ 181
5.18.4 Data Encoding and Bit Stuffing............................................................................ 181
5.18.5 Packet Formats.................................................................................................... 182
5.18.6 USB 2.0 Interrupts and Error Conditions ............................................................. 182
5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ........................................ 182
5.18.7 USB 2.0 Power Management .............................................................................. 183
5.18.7.1 Pause Feature ..................................................................................... 183
5.18.7.2 Suspend Feature ................................................................................. 183
5.18.7.3 ACPI Device States ............................................................................. 183
5.18.7.4 ACPI System States ............................................................................ 184
5.18.8 Interaction with UHCI Host Controllers ................................................................ 184
5.18.8.1 Port-Routing Logic ............................................................................... 185
5.18.8.2 Device Connects.................................................................................. 186
5.18.8.3 Device Disconnects ............................................................................. 186
5.18.8.4 Effect of Resets on Port-Routing Logic................................................ 187
5.18.9 USB 2.0 Legacy Keyboard Operation.................................................................. 187
5.18.10 USB 2.0 Based Debug Port ................................................................................. 187
5.18.10.1 Theory of Operation ............................................................................ 188
SMBus Controller (D31:F3) .............................................................................................. 192
5.19.1 Host Controller..................................................................................................... 192
5.19.1.1 Command Protocols ............................................................................ 193
5.19.2 Bus Arbitration ..................................................................................................... 196
5.19.3 Bus Timing........................................................................................................... 197
5.19.3.1 Clock Stretching................................................................................... 197
5.19.3.2 Bus Time Out (Intel® ICH8 as SMBus Master) .................................... 197
5.19.4 Interrupts / SMI# .................................................................................................. 198
5.19.5 SMBALERT# ....................................................................................................... 199
5.19.6 SMBus CRC Generation and Checking............................................................... 199
5.19.7 SMBus Slave Interface ........................................................................................ 199
5.19.7.1 Format of Slave Write Cycle ................................................................ 200
8 Intel® ICH8 Family Datasheet







NH82801HR equivalent, schematic
Contents
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11.1.12 SCMD_BAR—Secondary Command Block Base Address
Register (IDE D31:F1) ......................................................................................... 396
11.1.13 SCNL_BAR—Secondary Control Block Base Address Register (IDE D31:F1)... 396
11.1.14 BAR — Legacy Bus Master Base Address Register (SATA–D31:F2)................. 396
11.1.15 ABAR/SIDPBA1 — AHCI Base Address Register/Serial ATA Index
Data Pair Base Address (SATA–D31:F2)............................................................ 397
11.1.15.1 When CC.SCC is not 01h .................................................................... 397
11.1.15.2 When CC.SCC is 01h .......................................................................... 397
11.1.16 SVID—Subsystem Vendor Identification Register (SATA–D31:F2) .................... 398
11.1.17 SID—Subsystem Identification Register (SATA–D31:F2) ................................... 398
11.1.18 CAP—Capabilities Pointer Register (SATA–D31:F2).......................................... 398
11.1.19 INT_LN—Interrupt Line Register (SATA–D31:F2)............................................... 398
11.1.20 INT_PN—Interrupt Pin Register (SATA–D31:F2)................................................ 399
11.1.21 IDE_TIM — IDE Timing Register (SATA–D31:F2) .............................................. 399
11.1.22 SIDETIM—Slave IDE Timing Register (SATA–D31:F2)...................................... 401
11.1.23 SDMA_CNT—Synchronous DMA Control Register (SATA–D31:F2).................. 402
11.1.24 SDMA_TIM—Synchronous DMA Timing Register (SATA–D31:F2).................... 403
11.1.25 IDE_CONFIG—IDE I/O Configuration Register (SATA–D31:F2) ........................ 404
11.1.26 PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)..................................................................................... 405
11.1.27 PC—PCI Power Management Capabilities Register (SATA–D31:F2) ................ 405
11.1.28 PMCS—PCI Power Management Control and Status Register (SATA–D31:F2) 406
11.1.29 MSICI—Message Signaled Interrupt Capability Identification (SATA–D31:F2)... 406
11.1.30 MSIMC—Message Signaled Interrupt Message Control (SATA–D31:F2) .......... 407
11.1.31 MSIMA— Message Signaled Interrupt Message Address (SATA–D31:F2) ........ 408
11.1.32 MSIMD—Message Signaled Interrupt Message Data (SATA–D31:F2) .............. 408
11.1.33 MAP—Address Map Register (SATA–D31:F2) ................................................... 409
11.1.34 PCS—Port Control and Status Register (SATA–D31:F2) ................................... 410
11.1.35 SCLKCG—SATA Clock Gating Control Register ................................................ 411
11.1.36 SCLKGC—SATA Clock General Configuration Register .................................... 412
11.1.37 SIRI—SATA Indexed Registers Index Register................................................... 412
11.1.38 STRD—SATA Indexed Register Data Register................................................... 412
11.1.39 STTT1—SATA Indexed Registers Index 00h
(SATA TX Termination Test Register 1) .............................................................. 414
11.1.40 SIR18—SATA Indexed Registers Index 18h
(SATA Initialization Register 18h)........................................................................ 414
11.1.41 STME—SATA Indexed Registers Index 1Ch
(SATA Test Mode Enable Register) .................................................................... 414
11.1.42 SIR28—SATA Indexed Registers Index 28h
(SATA Initialization Register 28h)........................................................................ 415
11.1.43 SIR40—SATA Indexed Registers Index 40h
(SATA Initialization Register 40h)........................................................................ 415
11.1.44 STTT2—SATA Indexed Registers Index 74h
(SATA TX Termination Test Register 2) .............................................................. 415
11.1.45 SIR78—SATA Indexed Registers Index 78h
(SATA Initialization Register 78h)........................................................................ 416
11.1.46 SIR84—SATA Indexed Registers Index 84h
(SATA Initialization Register 84h)........................................................................ 416
11.1.47 SIR88—SATA Indexed Registers Index 88h
(SATA Initialization Register 88h)........................................................................ 416
16 Intel® ICH8 Family Datasheet










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