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PDF ( 数据手册 , 数据表 ) X9259

零件编号 X9259
描述 Quad Digitally-Controlled Potentiometers
制造商 Intersil Corporation
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X9259 数据手册, 描述, 功能
DATASHEET
Single Supply/Low Power/256-Tap/2-Wire Bus Quad
Digitally-Controlled (XDCP™) Potentiometers
X9259
The X9259 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2-wire bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and four nonvolatile
Data Registers that can be directly written to and read by the
user. The content of the WCR controls the position of the wiper.
At power-up, the device recalls the content of the default Data
Registers of each DCP (DR00, DR10, DR20, and DR30) to the
corresponding WCR.
The XDCP can be used as a three-terminal potentiometer or as
a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four separate potentiometers in one package
• 256 resistor taps–0.4% resolution
• 2-wire serial interface for write, read, and
transfer operations of the potentiometer
• Wiper resistance: 100Ω typical at VCC = 5V
• 4 nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper positions
• Standby current <5µA max
• VCC: 2.7V to 5.5V operation
• 50kΩ version of total resistance
• Endurance: 100,000 data changes per bit per register
• 100 year data retention
• Single supply version of X9258
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-Free (RoHS compliant)
Functional Diagram
VCC
RH0
RH1
RH2
RH3
A3
A2
A1
A0
SDA
SCL
2-WIRE
INTERFACE
POWER UP,
INTERFACE
CONTROL
AND
STATUS
WCR0
DR00
DR01
DR02
DR03
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
VSS
WP
RW0 RL0
RW1 RL1
RW2 RL2
RW3 RL3
December 12, 2014
FN8169.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2005-2007, 2014. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.







X9259 pdf, 数据表
X9259
Instructions
Four of the nine instructions are three bytes in length. These
instructions are:
• Read Wiper Counter Register – read the current wiper position
of the selected potentiometer.
• Write Wiper Counter Register – change current wiper position
of the selected potentiometer.
• Read Data Register – read the contents of the selected Data
Register.
• Write Data Register – write a new value to the selected Data
Register.
The basic sequence of the three byte instructions is illustrated in
Figure 5. These three-byte instructions exchange data between
the WCR and one of the Data Registers. A transfer from a Data
Register to a WCR is essentially a write to a static RAM, with the
static RAM controlling the wiper position. The response of the
wiper to this action is delayed by tWRL. A transfer from the WCR
(current wiper position), to a Data Register is a write to
nonvolatile memory and takes a minimum of tWR to complete.
The transfer can occur between one of the four potentiometer’s
WCR, and one of its associated registers, DRs; or it may occur
globally, where the transfer occurs between all potentiometers
and one associated register.
Four instructions require a two-byte sequence to complete. These
instructions transfer data between the host and the X9259;
either between the host and one of the data registers or directly
between the host and the Wiper Counter Register. These
instructions are:
• XFR Data Register to Wiper Counter Register – This transfers
the contents of one specified Data Register to the associated
Wiper Counter Register.
• XFR Wiper Counter Register to Data Register – This transfers
the contents of the specified Wiper Counter Register to the
specified associated Data Register.
• Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
• Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
Increment/Decrement Command
The final command is Increment/Decrement (Figures 6 and 7).
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9259 has
responded with an Acknowledge, the master can clock the
selected wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each SCL clock
pulse (tHIGH) while SDA is HIGH, the selected wiper moves one
wiper position towards the RH terminal. Similarly, for each SCL
clock pulse while SDA is LOW, the selected wiper moves one
resistor wiper position towards the RL terminal.
See “Instruction Format” on page 10 for more details.
SCL
SDA
0101
S ID3 ID2 ID1 ID0 A3
T
A
R
T
Device ID
A2 A1 A0
External
Address
A I3 I2 I1 I0
C
K
Instruction
Opcode
RB RA P1 P0 A
C
K
Register DCP/WCR
Address Address
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
S
T
O
P
SCL
SDA
0 101
S
T
ID3 ID2 ID1 ID0 A3
A
R Device ID
T
A2 A1 A0 A I3
C
External K
Address
I2 I1 I0
Instruction
Opcode
RB RA P1 P0 A
C
K
Register Pot/WCR
Address Address
D7 D6 D5 D4 D3 D2 D1 D0 A S
CT
Data for WCR[7:0] or DR[7:0]
KO
P
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE 2-WIRE INTERFACE
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FN8169.6
December 12, 2014







X9259 equivalent, schematic
XDCP Timing (for All Load Instructions)
X9259
SCL
SDA
VWx
LSB
tWRL
(STOP)
Write Protect and Device Address Pins Timing
SCL
SDA
(START)
(STOP)
tSU:WPA
...
(Any Instruction)
...
...
tHD:WPA
WP
A0, A1
Submit Document Feedback 16
FN8169.6
December 12, 2014










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