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PDF ( 数据手册 , 数据表 ) X9250

零件编号 X9250
描述 Quad Digitally Controlled Potentiometers
制造商 Intersil Corporation
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X9250 数据手册, 描述, 功能
®
Data Sheet
X9250
Low Noise/Low Power/SPI Bus/256 Taps
August 29, 2006
FN8165.3
Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Four potentiometers in one package
• 256 resistor taps/pot - 0.4% resolution
• SPI serial interface
• Wiper resistance, 40typical @ VCC = 5V
• Four nonvolatile data registers for each pot
• Nonvolatile storage of wiper position
• Standby current < 5µA max (total package)
• Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• 100k, 50ktotal pot resistance
• High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention - 100 years
• 24 Ld SOIC, 24 Ld TSSOP
• Dual supply version of X9251
• Pb-free plus anneal available (RoHS compliant)
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DESCRIPTION
The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array though the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V-
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
8
Data
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Pot 0
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW2/RW2
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VW1/RW1
Resistor
Array
Pot1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VW3/RW3
VH3/RH3
VL3/RH3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.







X9250 pdf, 数据表
Figure 8. Increment/Decrement Timing Limits
X9250
SCK
SI
tWRID
VW/RW
Voltage Out
INC/DEC CMD Issued
Table 1. Instruction Set
Instruction Set
Instruction
I3 I2 I1 I0 R1 R0 P1 P0
Operation
Read Wiper Counter
Register
1 0 0 1 0 0 P1 P0 Read the contents of the Wiper Counter
Register pointed to by P1- P0
Write Wiper Counter
Register
1 0 1 0 0 0 P1 P0 Write new value to the Wiper Counter Register
pointed to by P1- P0
Read Data Register
1 0 1 1 R1 R0 P1 P0 Read the contents of the Data Register
pointed to by P1- P0 and R1- R0
Write Data Register
1 1 0 0 R1 R0 P1 P0 Write new value to the Data Register pointed to
by P1- P0 and R1- R0
XFR Data Register to
Wiper Counter Register
1 1 0 1 R1 R0 P1 P0 Transfer the contents of the Data Register
pointed to by R1- R0 to the Wiper Counter
Register pointed to by P1- P0
XFR Wiper Counter
1 1 1 0 R1 R0 P1 P0 Transfer the contents of the Wiper Counter
Register to Data Register
Register pointed to by P1- P0 to the Register
pointed to by R1- R0
Global XFR Data Register 0 0 0 1 R1 R0 0
to Wiper Counter Register
0 Transfer the contents of the Data Registers
pointed to by R1- R0 of all four pots to their
respective Wiper Counter Register
Global XFR Wiper Counter 1 0 0 0 R1 R0 0
Register to Data Register
0 Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R1- R0 of all four pots
Increment/Decrement
Wiper Counter Register
0 0 1 0 0 0 P1 P0 Enable Increment/decrement of the Wiper
Counter Register pointed to by P1- P0
Read Status (WIP bit)
0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by
checking the WIP bit.
8 FN8165.3
August 29, 2006







X9250 equivalent, schematic
X9250
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
VWx
...
tWRID
...
SI ADDR
Inc/Dec
Inc/Dec
SO High Impedance
Write Protect and Device Address Pins Timing
...
CS (Any Instruction)
tWPASU
tWPAH
WP
A0
A1
16 FN8165.3
August 29, 2006










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