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PDF ( 数据手册 , 数据表 ) X40431

零件编号 X40431
描述 (X40430 / X40431) Triple Voltage Monitor
制造商 Xicor
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X40431 数据手册, 描述, 功能
Preliminary Information
4kbit EEPROM
X40430/X40431
Triple Voltage Monitor with Integrated CPU Supervisor
FEATURES
• Triple voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V/1.7V, 4.4V/2.6V/1.7V,
2.9V/1.7V/2.4V)
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three voltages or detect power fail
• Fault detection register
• Selectable power on reset timeout
• Selectable watchdog timer interval
• Debounced manual reset input
• Low power CMOS
—30µA typical standby current, watchdog on
—10µA typical standby current, watchdog off
• 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
www.DataSheet4U.com — 5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, 1/4, 1/2, all of EEPROM
• 400kHz I2C interface
• 2.4V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
BLOCK DIAGRAM
DESCRIPTION
The X40430/31 combines power-on reset control,
watchdog timer, supply voltage supervision, secondary
and third voltage supervision, manual reset, and Block
Lockprotect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point. RESET/
RESET is active until VCC returns to proper operating
level and stabilizes. A second and third voltage monitor
circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Xicor’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
V3MON
V2MON
V3 Monitor
Logic
+
VTRIP3
-
V2 Monitor
Logic
+
VTRIP2
-
V3FAIL
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
Data
Register
Command
Decode Test
& Control
Logic
REV 1.2.3 11/28/00
Fault Detection
Register
Status
Register
EEPROM
Array
VCCLoMgoicnitor
+
VTRIP1
-
www.xicor.com
Watchdog
and
Reset Logic
WDO
MR
Power on,
Manual Reset
Low Voltage
Reset
Generation
RESET
X40430
RESET
X40431
LOWLINE
Characteristics subject to change without notice. 1 of 24







X40431 pdf, 数据表
X40430/X40431 – Preliminary Information
BP1, BP0: Block Protect Bits (Nonvolatile)
The Block Protect Bits, BP1 and BP0, determine which
blocks of the array are write protected. A write to a pro-
tected block of memory is ignored. The block protect
bits will prevent write operations to one of eight seg-
ments of the array.
00
01
10
11
Protected Addresses
(Size)
None
180h – 1FFh (128 bytes)
100h – 1FFh (256 bytes)
000h – 1FFh (512 bytes)
Array Lock
None
Upper 1/4 (Q4)
Upper 1/2 (Q3,Q4)
Full Array (All)
PUP1, PUP0: Power Up Bits (Nonvolatile)
The Power Up bits, PUP1 and PUP0, determine the
tPURST time delay. The nominal power up times are
shown in the following table.
PUP1
0
0
1
1
PUP0
0
1
0
1
Power on Reset Delay (tPURST)
50ms
200ms
400ms
800ms
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1
0
0
1
1
WD0
0
1
0
1
Watchdog Time Out Period
1.4 seconds
200 milliseconds
25 milliseconds
disabled
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a start and ended with a stop).
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
– Write one byte value to the Control Register that has
all the control bits set to the desired state. The Con-
trol register can be represented as qxys t01r in
binary, where xy are the WD bits, and st are the BP
bits and qr are the power up bits. This operation pro-
ceeded by a start and ended with a stop bit. Since
this is a nonvolatile write cycle it will take up to 10ms
(max.) to complete. The RWEL bit is reset by this
cycle and the sequence must be repeated to change
the nonvolatile bits again. If bit 2 is set to ‘1’ in this
third step (qxys t11r) then the RWEL bit is set, but
the WD1, WD0, PUP1, PUP0, BP1 and BP0 bits
remain unchanged. Writing a second byte to the con-
trol register is not allowed. Doing so aborts the write
operation and returns a NACK.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits in the Control Register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
Fault Detection Register (FDR)
The Fault Detection Register provides the user the
status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
Low Voltage Fail bits are volatile
7 6 5 4 3 210
LV1F LV2F LV3F WDF MRF 0 0 0
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
There is no need to set the WEL or RWEL in the
control register to access this FDR.
REV 1.2.3 11/28/00
www.xicor.com
Characteristics subject to change without notice. 8 of 24







X40431 equivalent, schematic
X40430/X40431 – Preliminary Information
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
Symbol
Parameter
Second Supply Monitor
IV2 V2MON Current
VTRIP2 V2MON Trip Point Voltage
VV2H V2MON Hysteresis
Third Supply Monitor
IV3
VTRIP3
VV3H
V3MON Current
V3MON Trip Point Voltage
V3MON Hysteresis
Min. Typ.(4) Max.
15
1.7 4.75
60
15
1.7 4.75
60
Unit
µA
V
mV
µA
V
mV
Test Conditions
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that ini-
tiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address
Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
(4) At 25°C, VCC = 3V
CAPACITANCE
Symbol
COUT(1)
CIN(1)
Parameter
Output Capacitance (SDA, RESET/RESET, LOWLINE,
V2FAIL,V3FAIL, WDO)
Input Capacitance (SCL, WP, MR)
Max.
8
6
Unit
pF
pF
Test Conditions
VOUT = 0V
VIN = 0V
Note: (1) This parameter is not 100% tested.
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
VCC = 5V
5V VCC V2MON, V3MON
SDA
2.06K
30pF
RESET
WDO
4.6K
4.6K
V2FAIL,
V3FAIL
30pF
30pF
A.C. TEST CONDITIONS)
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard output load
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
REV 1.2.3 11/28/00
www.xicor.com
Characteristics subject to change without notice. 16 of 24










页数 24 页
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