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PDF ( 数据手册 , 数据表 ) X40430

零件编号 X40430
描述 (X40430 - X40435) Triple Voltage Monitor
制造商 Intersil Corporation
LOGO Intersil Corporation LOGO 


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X40430 数据手册, 描述, 功能
X40430, X40431, X40434, X40435
® 4Kbit EEPROM
Data Sheet
July 29, 2005
FN8251.0
Triple Voltage Monitor with Integrated
CPU Supervisor
FEATURES
• Monitoring voltages: 5V to 9V
• Independent core voltage monitor
• Triple voltage detection and reset assertion
—Standard reset threshold settings. See selec-
tion table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three separate voltages
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• Memory security
www.DataSheet4U.com 4Kbits of EEPROM
—16 byte page write mode
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
— Computers
—Network Servers
DESCRIPTION
The X40430, X40431, X40434, X40435 combines
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision,
manual reset, and Block Lockprotect serial EEPROM
in one package. This combination lowers system cost,
reduces board space requirements, and increases
reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system
when VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second and third volt-
age monitor circuit tracks the unregulated supply to
provide a power fail warning or monitors different
power supply voltage. Three common low voltage
combinations are available. However, Intersil’s unique
circuits allows the threshold for either voltage monitor
to be reprogrammed to meet specific system level
requirements or to fine-tune the threshold for applica-
tions requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection.
The array is internally organized as x 8. The device
features a 2-wire interface and software protocol
allowing operation on an I2C bus.
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.







X40430 pdf, 数据表
X40430, X40431, X40434, X40435
PUP1, PUP0: Power-up Bits (Nonvolatile)
The Power-up bits, PUP1 and PUP0, determine the
tPURST time delay. The nominal power-up times are
shown in the following table.
PUP1
0
0
1
1
PUP0
0
1
0
1
Power-on Reset Delay (tPURST)
50ms
200ms (factory setting)
400ms
800ms
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1
0
0
1
1
WD0
0
1
0
1
Watchdog Time Out Period
1.4 seconds
200 milliseconds
25 milliseconds
disabled (factory setting)
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceded by a start and ended with a stop).
– Write a 06H to the Control Register to set the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
– Write one byte value to the Control Register that has
all the control bits set to the desired state. The Con-
trol register can be represented as qxys 001r in
binary, where xy are the WD bits, s is the BP bit and
qr are the power-up bits. This operation proceeded
by a start and ended with a stop bit. Since this is a
Figure 7. Valid Data Changes on the SDA Bus
nonvolatile write cycle it will take up to 10ms (max.)
to complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to ‘1’ in this third step
(qxys 011r) then the RWEL bit is set, but the WD1,
WD0, PUP1, PUP0, and BP bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
Notes: 1. tPURST is set to 200ms as factory default.
2. Watch Dog Timer bits are shipped disabled.
FAULT DETECTION REGISTER
The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and Three
Low Voltage Fail bits are volatile
7 6 5 4 3 210
LV1F LV2F LV3F WDF MRF 0 0 0
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
There is no need to set the WEL or RWEL in the
control register to access this FDR.
SCL
SDA
Data Stable
Data Change
Data Stable
8 FN8251.0
July 29, 2005







X40430 equivalent, schematic
X40430, X40431, X40434, X40435
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
Symbol
Parameter
VCC Supply
VTRIP1(5) VCC Trip Point Voltage Range
Min Typ (4) Max
2.0 4.75
4.55 4.6 4.65
Second Supply Monitor
IV2 V2MON Current
VTRIP2(5) V2MON Trip Point Voltage Range
tRPD2(6) VTRIP2 to V2FAIL
Third Supply Monitor
IV3 V3MON Current
VTRIP3(5) V3MON Trip Point Voltage Range
tRPD3(6) VTRIP3 to V3FAIL
4.35 4.4 4.45
2.85 2.9 2.95
15
1.7 4.75
0.9 3.5
2.85 2.9 2.95
2.55 2.6 2.65
2.15 2.2 2.25
1.25 1.3 1.35
0.95 1.0 1.05
5
15
1.7 4.75
1.65 1.7 1.75
3.05 3.1 3.15
2.85 2.9 2.95
5
Unit Test Conditions
V
V X40430, X40431-A, X40434,
X40435
V X40430, X40431-B
V X40430, X40431-C
µA
V x40430, X40431
V x40434, X40435
V X40430, X40431-A
V X40430, X40431-B
V X40430, X40431-C
V X40434, X40435-A&B
V X40434, X40435-C
µs
µA
V
V X40430, X40431
V X40434, X40435-A
V X40434, X40435-B&C
µs
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high
voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
(4) At 25°C, VCC = 3V
(5) See ordering information for standard programming levels. For custom programmed levels, contact factory.
(6) Based on characterization data.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2, 3)
R
V Vref VxMON
+
C VREF
Output Pin
tRPDX = 5µs worst case
CAPACITANCE
Symbol
Parameter
COUT(1)
Output Capacitance (SDA, RESET/RESET, LOWLINE,
V2FAIL,V3FAIL, WDO)
CIN(1)
Input Capacitance (SCL, WP, MR)
Note: (1) This parameter is not 100% tested.
Max
8
6
V = 100mV
Unit
pF
pF
Test Conditions
VOUT = 0V
VIN = 0V
16 FN8251.0
July 29, 2005










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