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PDF ( 数据手册 , 数据表 ) X4043

零件编号 X4043
描述 (X4043 / X4045) CPU Supervisor
制造商 Intersil Corporation
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X4043 数据手册, 描述, 功能
®
Data Sheet
September 30, 2005
X4043, X4045
4k, 512 x 8 Bit
FN8118.1
CPU Supervisor with 4kbit EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 4kbits of EEPROM
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes
of EEPROM array with Block Lockprotection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
www.DataSheet4U.com Available packages
—8 Ld SOIC
—8 Ld MSOP
—8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
DESCRIPTION
The X4043/45 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock Protect Serial
EEPROM Memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
EEPROM Array
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET (X4043)
RESET (X4045)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.







X4043 pdf, 数据表
X4043, X4045
Figure 5. VTRIP Programming Sequence
VTRIP Programming
No Desired
VTRIP <
Present Value ?
YES
Execute
VTRIP Reset Sequence
New VCC applied =
Old VCC applied + | Error |
Set VCC = desired VTRIP
Execute
Set Higher VTRIP Sequence
Power-down
the Device
Let: MDE = Maximum Desired Error
MDE+
Desired Value
MDE
Acceptable
Error Range
Error = Actual – Desired
New VCC applied =
Old VCC applied – | Error |
Execute Reset VTRIP
Sequence
NO
Error < MDE
Ramp VCC
Output Switches?
(RESET)
YES
Actual VTRIP
Desired VTRIP
= Error
| Error | < | MDE |
Error > MDE+
DONE
Control Register
The control register provides the user a mechanism for
changing the block lock and watchdog timer settings.
The block lock and watchdog timer bits are nonvolatile
and do not change when power is removed.
The control register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte
write operation directly to the address of the register
and only one data byte is allowed for each register
write operation. Prior to writing to the control register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Register".
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X4043/45 will
not acknowledge any data bytes written after the first
byte is entered.
8 FN8118.1
September 30, 2005







X4043 equivalent, schematic
X4043, X4045
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with
respect to VSS ...................................... -1.0V to +7V
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds) ........ 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
-40°C
Max.
70°C
+85°C
Option
-2.7 and -2.7A
Blank and -4.5A
Supply Voltage Limits
2.7V to 5.5V
4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Symbol
ICC1(1)
ICC2(1)
ISB1(2)
Parameter
Active supply current read
Active supply current write
Standby current AC (WDT off)
ISB2(2) Standby current DC (WDT off)
ISB3(2) Standby current DC (WDT on)
ILI Input leakage current
ILO Output leakage current
VIL(3)
VIH(3)
VHYS
VOL
Input LOW voltage
Input nonvolatile
Schmitt trigger input hysteresis
Fixed input level
VCC related level
Output LOW voltage
VCC = 2.7 to 5.5V
Min.
Max.
1.0
3.0
1
1
20
10
10
-0.5 VCC x 0.3
VCC x 0.7 VCC + 0.5
Unit
mA
mA
µA
µA
µA
µA
µA
V
V
Test Conditions
VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL = 400kHz
VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL= 400kHz, SDA = open
VCC = 1.22 x VCC min
VSDA = VSCL = VSB
Others = GND or VSB
VSDA =VSCL = VSB
Others = GND or VSB
VIN = GND to VCC
VSDA = GND to VCC
device is in standby
0.2
.05 x VCC
0.4
V
V
V IOL = 3.0mA (2.7-5.5V)
IOL = 1.8mA (2.0-3.6V)
Notes: (1) The device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave
address byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a
nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave address byte.
(3) VIL min. and VIH max. are for reference only and are not tested.
16 FN8118.1
September 30, 2005










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