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PDF ( 数据手册 , 数据表 ) X40414

零件编号 X40414
描述 (X40410 - X40415) Dual Voltage Monitor
制造商 Intersil Corporation
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X40414 数据手册, 描述, 功能
®
Data Sheet
X40410, X40411, X40414, X40415
4kbit EEPROM
March 28, 2005
FN8116.0
Dual Voltage Monitor with Integrated CPU
Supervisor
FEATURES
• Dual voltage detection and reset assertion
—Standard reset threshold settings
See Selection table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power-on reset timeout (0.05s,
0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms,
200ms,1.4s, off)
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 4Kbits of EEPROM
—16 byte page write mode
—5ms write cycle time (typical)
www.DataSheet4U.com
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect none or 1/2 of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
BLOCK DIAGRAM
• Available packages
—8-lead SOIC, TSSOP
• Monitor Voltages: 5V to 0.9V
• Memory Security
• Independent Core Voltage Monitor
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
— Computers
—Network Servers
DESCRIPTION
The X40410/11/14/15 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary voltage supervision, and Block Lockpro-
tect serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
SDA
SCL
VCC
(V1MON)
V2MON
Data
Register
Command
Decode Test
& Control
Logic
Threshold
Reset Logic
Fault Detection
Register
Status
Register
EEPROM
Array
Watchdog Timer
and
Reset Logic
User Programmable
VTRIP1
User Programmable
VTRIP2
+
-
VCC or
+ V2MON
Power-on,
Low Voltage
Reset
Generation
-
*X40410/11= V2MON*
X40414/15 = VCC
WDO
RESET
X40410/14
RESET
X40411/15
V2FAIL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.







X40414 pdf, 数据表
X40410, X40411, X40414, X40415
Figure 6. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
At power-up, the Fault Detection Register is defaulted
to all “0”. The system needs to initialize this register to
all “1” before the actual monitoring take place. In the
event of any one of the monitored sources failed. The
corresponding bits in the register will change from a
“1” to a “0” to indicate the failure. At this moment, the
system should perform a read to the register and
noted the cause of the reset. After reading the register
the system should reset the register back to all “1”
again. The state of the Fault Detection Register can be
read at any time by performing a random read at
address 0FFh, using the special preamble.
The FDR can be read by performing a random read at
OFFh address of the register at any time. Only one
byte of data is read by the register read operation.
WDF, Watchdog Timer Fail Bit (Volatile)
The WDF bit will set to “0” when the WDO goes active.
LV1F, Low VCC Reset Fail Bit (Volatile)
The LV1F bit will be set to “0” when VCC (V1MON)
falls below VTRIP1.
LV2F, Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls
below VTRIP2.
SERIAL INTERFACE
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 6.
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.
Serial Stop Condition
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. (See Figure 6).
8 FN8116.0
March 28, 2005







X40414 equivalent, schematic
X40410, X40411, X40414, X40415
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR
VCC = 5V
5V
VOUT
V2MON
2.06k
SDA
30pF
RESET
WDO
4.6k
V2FAIL
30pF
4.6k
30pF
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard output load
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
16 FN8116.0
March 28, 2005










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