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PDF ( 数据手册 , 数据表 ) X4005

零件编号 X4005
描述 (X4003 / X4005) CPU Supervisor
制造商 Intersil Corporation
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X4005 数据手册, 描述, 功能
®
Data Sheet
X4003, X4005
May 11, 2006
FN8113.1
CPU Supervisor
FEATURES
• Selectable watchdog timer
—Select 200ms, 600ms, 1.4s, off
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
nominal 4.62V, 4.38V, 2.92V, 2.68V, 1.75V
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—12µA typical standby current, watchdog on
—800nA typical standby current watchdog off
—3mA active current
• 400kHz I2C interface
• 1.8V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld MSOP
• Pb-free plus anneal available (RoHS compliant)
www.DataSheet4U.com
BLOCK DIAGRAM
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Control
Register
VTRIP
+
-
DESCRIPTION
These devices combine three popular functions,
Power-on Reset Control, Watchdog Timer, and Supply
Voltage Supervision. This combination lowers system
cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent
protection mechanism for microcontrollers. When the
microcontroller fails to restart a timer within a select-
able time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available; however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements, or to fine-tune the thresh-
old for applications requiring higher precision.
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET (X4003)
RESET (X4005)
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.







X4005 pdf, 数据表
X4003, X4005
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
control register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the control register
during a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL
bit is LOW, writes the control register will be ignored
(no acknowledge will be issued after the data byte).
The WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
watchdog timer. The options are shown below.
WD1
0
0
1
1
WD0
0
1
0
1
Watchdog Time Out Period
1.4 seconds
600 milliseconds
200 milliseconds
Disabled (factory setting)
Writing to the Control Register
Changing any of the nonvolatile bits of the control regis-
ter requires the following steps:
– Write a 02H to the control register to set the write
enable latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop.)
– Write a 06H to the control register to set both the
register write enable latch (RWEL) and the WEL bit.
This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop.)
– Write a value to the control register that has all the
control bits set to the desired state. This can be rep-
resented as 0xy0 0010 in binary, where xy are the
WD bits. (Operation preceeded by a start and ended
with a stop.) Since this is a nonvolatile write cycle it
will take up to 10ms to complete. The RWEL bit is
reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2
is set to ‘1’ in this third step (0xy0 0110) then the
RWEL bit is set, but the WD1 and WD0 bits remain
unchanged. Writing a second byte to the control reg-
ister is not allowed. Doing so aborts the write opera-
tion and returns a NACK.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the control register to 0. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged
and the RWEL bit remains set.
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
8 FN8113.1
May 11, 2006







X4005 equivalent, schematic
X4003, X4005
RESET/RESET Output Timing
Symbol
Parameter
tWDO
tCST
tRST
Watchdog time out period,
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
CS pulse width to reset the watchdog
Reset time out
VTRIP Programming Timing Diagram
tTHD
tTSU
VTRIP
Min.
100
450
1
400
100
Typ.
OFF
200
600
1.4
200
Max.
300
800
2
400
Unit
ms
ms
sec
ns
ms
(VVTCRCIP)
VP
WP
tVPO
tRP
tVPH
00h
01h or 03h
tVPS
A0h
SCL
SDA
VTRIP Programming Parameters
Parameter
Description
tVPS
tVPH
tTSU
tTHD
tWC
tVPO
tRP
VP
VTRAN
Vta1
Vta2
VTRIP program enable voltage setup time
VTRIP program enable voltage hold time
VTRIP setup time
VTRIP hold (stable) time
VTRIP write cycle time
VTRIP program enable voltage off time (between successive adjustments)
VTRIP program recovery period (between successive adjustments)
Programming voltage
VTRIP programmed voltage range
Initial VTRIP program voltage accuracy (VCC applied - VTRIP) (Programmed at 25°C.)
Subsequent VTRIP program voltage accuracy [(VCC applied - Vta1) - VTRIP.
Programmed at 25°C.)
Vtr VTRIP program voltage repeatability (Successive program operations. Programmed
at 25°C.)
Vtv VTRIP program variation after programming (0-75°C). (programmed at 25°C)
VTRIP programming parameters are periodically sampled and are not 100% tested.
Min.
1
1
1
10
0
10
15
1.7
-0.1
-25
Max.
10
18
5.0
+0.4
+25
Unit
µs
µs
µs
ms
ms
µs
ms
V
V
V
mV
-25 +25 mV
-25 +25 mV
16 FN8113.1
May 11, 2006










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