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PDF ( 数据手册 , 数据表 ) PX3511B

零件编号 PX3511B
描述 Advanced Synchronous Rectified Buck MOSFET Drivers
制造商 Intersil Corporation
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PX3511B 数据手册, 描述, 功能
®
Data Sheet
Advanced Synchronous Rectified Buck
MOSFET Drivers with Protection Features
The PX3511A and PX3511B are high frequency MOSFET
drivers specifically designed to drive upper and lower power
N-Channel MOSFETs in a synchronous rectified buck
converter topology. These drivers combined with the
ISL6595 Digital Multi-Phase Buck PWM controller and
N-Channel MOSFETs form a complete core-voltage
regulator solution for advanced microprocessors.
The PX3511A drives the upper gate to 12V, while the lower
gate can be independently driven over a range from 5V to
12V. The PX3511B drives both upper and lower gates over a
range of 5V to 12V. This drive-voltage provides the flexibility
necessary to optimize applications involving trade-offs
between gate charge and conduction losses.
An adaptive zero shoot-through protection is integrated to
prevent both the upper and lower MOSFETs from conducting
simultaneously and to minimize the dead time. These
products add an overvoltage protection feature operational
before VCC exceeds its turn-on threshold, at which the
PHASE node is connected to the gate of the low side
MOSFET (LGATE). The output voltage of the converter is
then limited by the threshold of the low side MOSFET, which
provides some protection to the microprocessor if the upper
MOSFET(s) is shorted during initial start-up.
These drivers also feature a three-state PWM input which,
working together with Intersil’s multi-phase PWM controllers,
prevents a negative transient on the output voltage when the
output is shut down. This feature eliminates the Schottky
diode that is used in some systems for protecting the load
from reversed output voltage events.
PX3511A, PX3511B
February 26, 2007
FN6462.0
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Adjustable Gate Voltage (5V to 12V) for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 2MHz)
- 3A Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Three-State PWM Input for Output Stage Shutdown
• Three-State PWM Input Hysteresis for Applications With
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper Pad for Enhanced Heat
Sinking
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Core Regulators for Intel® and AMD® Microprocessors
• High Current DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB417 for Power Train Design, Layout
Guidelines, and Feedback Compensation Design
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.







PX3511B pdf, 数据表
PX3511A, PX3511B
driver current can be estimated with Equations 2 and 3,
respectively,
PQg_TOT = PQg_Q1 + PQg_Q2 + IQ VCC
P Q g _Q1
=
Q-----G-----1---------U----V-----C-----C----2--
VGS1
FS
W
NQ
1
PQ g _Q2
=
Q-----G-----2---------L---V-----C-----C----2--
VGS2
FSW
NQ2
(EQ. 2)
IDR
=
Q-----G-----1---------U----V-----C-----C----------N----Q-----1-
VGS1
+
-Q----G-----2---------LV---V--G---C-S----C2----------N----Q-----2-⎠⎟⎞
FSW + IQ
(EQ. 3)
where the gate charge (QG1 and QG2) is defined at a
particular gate to source voltage (VGS1and VGS2) in the
corresponding MOSFET datasheet; IQ is the driver’s total
quiescent current with no load at both drive outputs; NQ1
and NQ2 are number of upper and lower MOSFETs,
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The IQ*VCC
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (RG1 and RG2) and the internal gate resistors
(RGI1 and RGI2) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
PDR = PDR_UP + PDR_LOW + IQ VCC
(EQ. 4)
P D R _UP
=
-------------R-----H----I--1--------------
RHI1 + REXT1
+
R-----L---O-----1R----+-L---O-R----1-E----X----T---1- ⎠⎟⎞
P-----Q----g----_--Q-----1-
2
P D R _LOW
=
-------------R-----H----I--2--------------
RHI2 + REXT2
+
R-----L---O-----2R----+-L---O-R----2-E----X----T---2- ⎠⎟⎞
P-----Q----g----_--Q-----2-
2
REXT1
=
RG
1
+
R-----G-----I-1--
NQ1
REXT2
=
RG2
+
R-----G-----I-2--
NQ2
UVCC
BOOT
RHI1
RLO1
PHASE
CGD
G
RG1
RGI1
CGS
S
D
CDS
Q1
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
LVCC
RHI2
RLO2
CGD
G
RG2
RGI2
CGS
S
D
CDS
Q2
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
8 FN6462.0
February 26, 2007














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