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PDF ( 数据手册 , 数据表 ) ISL12021

零件编号 ISL12021
描述 Real Time Clock
制造商 Intersil Corporation
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ISL12021 数据手册, 描述, 功能
ISL12021
®
Real Time Clock with On Chip Temp Compensation ±5ppm
Data Sheet
March 30, 2007
FN6451.0
Low Power RTC with VDD Battery Backed
SRAM and Embedded Temp
Compensation ±5ppm with Auto Day Light
Saving
The ISL12021 device is a low power real time clock with an
embedded Temp sensor for oscillator compensation,
clock/calendar, power fail, low battery monitor, brown out
indicator, single periodic or polled alarms, intelligent battery
backup switching and 128 bytes of battery-backed user
SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Daylight Savings time adjustment is done automatically,
using parameters entered by the user. Power fail and battery
monitors offer user-selectable trip levels. A time stamp
function records the time and date of switchover from VDD to
battery power, and also from battery to VDD power.
Pinoutwww.DataSheet4U.com
ISL12021
(14 LD TSSOP)
TOP VIEW
NC
X1
X2
VBAT
GND
LVRST
NC
1
2
3
4
5
6
7
14 NC
13 VDD
12 IRQ
11 SCL
10 SDA
9 FOUT
8 NC
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• On-chip Oscillator Compensation Over the Operating
Temp Range
- ±5ppm over -20°C to +70°C
• Day Light Saving Time
- Customer Programmable
• Separate FOUT pin
- 15 Selectable Frequency Outputs
• 1 Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
- Dedicated IRQ output pin
• Automatic Backup to Battery or Super Cap
- Operation to VBAT = 1.8V
- 1.0µA Battery Supply Current
• Battery Status Monitor, 2 Levels, Selectable by Customer
to:
- Seven Selectable Voltages for Each Level
• Power status Brown Out Monitor
- Six selectable trip level, from 4.675V to 2.295V
- Separate Low Voltage LVRST pin
• Time Stamp during Power to Battery and Battery to Power
Cross Over
- Time Stamp. First VDD to VBAT, and Last VBAT to VDD
• 128 Bytes Battery-Backed User SRAM
• I2C Interface
- 400kHz Clock Frequency
• 14 Ld TSSOP package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• POS Equipment
• Medical Application
• Security Related Application
• Vending Machine
• White Goods
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.







ISL12021 pdf, 数据表
ISL12021
Brown Out Detection
The ISL12021 monitors the VDD level continuously and
provides warning if the VDD level drops below the prescribed
levels. There are five (5) levels that could be selected for the
trip level. Typically set at the 85% of nominal VDD level. The
Real Time Clock Power Brown Out Bit ( LVDD) is set once
the VDD level drops below the trip point. The LVRST output
becomes active when the Power Brown Out Bit is set.
When the VDD power is re-established and is above the
85%VDD + 50mV trip point, the VPBM0 is set. The LVDD bit
is reset once it is read by the CPU. Note: The I2C comm link
remains active unless the Battery VTRIP levels are reached.
Battery Level Monitor
The ISL12021 has a built in warning feature once the Back
Up battery level drops first to 85% and then to 75% of the
battery’s nominal VBAT level. When the battery voltage
drops to between 85% and 75%, the LBAT85 bit is set in the
status register. When the level drops below 75%, both
LBAT85 and LBAT75 bits are set in the status register.
There is a Battery Timestamp Function available. Once the
VDD is low enough to enable switchover to the battery, the
RTC time/date are written into the TSVTB register. This
information can be read from the TSVTB registers to
discover the point in time of the VDD powerdown. If there are
multiple powerdown cycles before reading these registers,
the first values stored in these registers will be retained.
These registers will hold the original powerdown value until
they are cleared by writing “00h” to each register.
Low Power Mode
The normal power switching of the ISL12021 is designed to
switch into battery backup mode only if the VDD power is
lost. This will ensure that the device can accept a wide range
of backup voltages from many types of sources while reliably
switching into backup mode. Another mode (called Low
Power Mode) is available to allow direct switching from VDD
to VBAT without requiring VDD to drop below VTRIP. Since
the additional monitoring of VDD vs VTRIP is no longer
needed, that circuitry is shut down and less power is used
while operating from VDD. Power savings are typically
600nA at VDD = 5V. Low Power Mode is activated via the
BSW bit in the control and status registers.
Low Power Mode is useful in systems where VDD is normally
higher than VBAT at all times. The device will switch from
VDD to VBAT when VDD drops below VBAT, with about 50mV
of hysteresis to prevent any switchback of VDD after
switchover. In a system with VDD = 5V and backup lithium
battery of VBAT = 3V, Low Power Mode can be used.
However, it is not recommended to use Low Power Mode in
a system with VDD = 3.3V ±10%, VBAT 3.0V, and when
there is a finite I-R voltage drop in the VDD line.
Real Time Clock Operation
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representation
of second, minute, hour, day of week, date, month, and year.
The RTC also has leap-year correction. The clock also
corrects for months having fewer than 31 days and has a bit
that controls 24 hour or AM/PM format. When the ISL12021
powers up after the loss of both VDD and VBAT, the clock will
not begin incrementing until at least one byte is written to the
clock register.
Single Event and Interrupt
The alarm mode is enabled via the MSB bit. Choosing single
event or interrupt alarm mode is selected via the IM bit. Note
that when the frequency output function is enabled, the
alarm function is disabled.
The standard alarm allows for alarms of time, date, day of
the week, month, and year. When a time alarm occurs in
single event mode, an IRQ pin will be pulled low and the
alarm status bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring
alarm functionality. Hence, once the alarm is set, the device
will continue to alarm for each occurring match of the alarm
and present time. Thus, it will alarm as often as every minute
(if only the nth second is set) or as infrequently as once a
year (if at least the nth month is set). During pulsed interrupt
mode, the IRQ pin will be pulled low for 250ms and the alarm
status bit (ALM) will be set to “1”.
The ALM bit can be reset by the user or cleared
automatically using the auto reset mode (see ARST bit). The
alarm function can be enabled/disabled during battery
backup mode using the FOBATB bit. For more information
on the alarm, please see “ALARM Registers (10h to 15h)” on
page 16.
Frequency Output Mode
The ISL12021 has the option to provide a clock output signal
using the FOUT open drain output pin. The frequency output
mode is set by using the FO bits to select 15 possible output
frequency values from 1/32Hz to 32kHz. The frequency
output can be enabled/disabled during battery backup mode
using the FOBATB bit.
General Purpose User SRAM
The ISL12021 provides 128 bytes of user SRAM. The SRAM
will continue to operate in battery backup mode. However, it
should be noted that the I2C bus is disabled in battery
backup mode.
I2C Serial Interface
The ISL12021 has an I2C serial bus interface that provides
access to the control and status registers and the user
SRAM. The I2C serial interface is compatible with other
industry I2C serial bus protocols using a bi-directional data
signal (SDA) and a clock signal (SCL).
8 FN6451.0
March 30, 2007







ISL12021 equivalent, schematic
ISL12021
TABLE 15. FREQUENCY OF TEMPERATURE SENSING AND
CORRECTION BIT
BTSE
BTSR
TC PERIOD IN
BATTERY MODE
0 0 OFF
0 1 OFF
1 0 10 Minutes
1 1 1 Minute
GAIN FACTOR OF ATR BIT (BETA)<3:0>
Beta is specified to take care of the Cm variations of the
crystal. Most crystals specify Cm around 2.2fF. For example,
if Cm > 2.2fF, the actual ATR steps may reduce from
1ppm/step to approximately 0.80ppm/step. Beta is then used
to adjust for this variation and restore the step size to
1ppm/step.
The value for BETA should only be changed while the TSE
(Temp Sense Enable) bit is “0”. The procedure for writing the
BETA register involves two steps. First, Write the new value
of BETA with TSE = 0. Then Write the same value of BETA
with TSE = 1. This will insure the next temp sense cycle will
use the new BETA value. BETA values are limited in the
range from 0100 to 1100 as shown in Table 16.
TABLE 16. BETA VALUES
BETA<3:0>
ATR STEP ADJUSTMENT
0100
0.500
0101
0.625
0110
0.750
0111
0.875
1000
1.00
1001
1.125
1010
1.250
1011
1.375
1100
1.500
Final Analog Trimming Register (FATR)
This register shows the final setting of ATR after temperature
correction. It is read-only, the user cannot overwrite a value
to this register. This value is accessible as a means of
monitoring the temperature compensation function. See
Table 17.
TABLE 17. FINAL ANALOG TRIMMING REGISTER
ADDR 7 6 5 4 3 2 1 0
0Eh 0 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0
Final Digital Trimming Register (FDTR)
This Register shows the final setting of DTR after
temperature correction. It is read-only, the user cannot
overwrite a value to this register. The value is accessible as
a means of monitoring the temperature compensation
function. The corresponding clock adjustment values are
shown in Table 19. The DTR setting is only positive as it is
used to correct for the negative drift of a normal crystal over
temperature.
TABLE 18. FINAL DIGITAL TRIMMING REGISTER
ADDR 7 6 5 4 3
2
1
0
0Fh FDTR2 FDTR1 FDTR0
TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL
DIGITAL TRIMMING REGISTER
DTR<2:0>
DECIMAL
ppm
ADJUSTMENT
000 0 0
001 1 32
010 2 64
011 3 96
100 4 128
101 5 160
110 6 196
111 7 -32
ALARM Registers (10h to 15h)
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
Single Event Mode is enabled by setting the bit 7 on any
of the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit
to “0”, and disabling the frequency output. This mode
permits a one-time match between the Alarm registers
and the RTC registers. Once this match occurs, the ALM
bit is set to “1” and the IRQ output will be pulled low and
will remain low until the ALM bit is reset. This can be done
manually or by using the auto-reset feature.
Interrupt Mode is enabled by setting the bit 7 on any of
the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to
16 FN6451.0
March 30, 2007










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