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PDF ( 数据手册 , 数据表 ) COM20051I

零件编号 COM20051I
描述 Integrated Microcontroller and ARCNET (ANSI 878.1) Interface
制造商 SMSC Corporation
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COM20051I 数据手册, 描述, 功能
COM20051I
Integrated Microcontroller and
ARCNET (ANSI 878.1) Interface
!" High Performance/Low Cost
!" Microcontroller Based on Popular 8051
Architecture
!" Intel 8051 Instruction Set Compatible
!" Drop-In Replacement for 80C32 PLCC
!" Network Supports up to 255 Nodes
!" Powerful Network Diagnostics
!" Maximum 507 Byte Packets
!" Duplicate Node ID Detection
!" Self-Configuring Network Protocol
FEATURES
!" Retains all 8051 Peripherals Including Serial I/O
and Two Timers
!" Utilizes ARCNET Token Bus Network Engine
!" Requires No Special Emulators
!" 5 Mbps to 156 Kbps Network Data Rate
!" Network Interface Supports RS-485, Twisted Pair,
Coaxial, and Fiber Optic Interfaces
!" Receive All Mode Allows Any Packet to Be
Received
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GENERAL DESCRIPTION
The COM20051I is a low-cost, highly-integrated microcontroller incorporating a high-performance network controller
based on the ARCNET Token Bus Standard (ANSI 878.1). The COM20051I is based around the popular Intel 8051
architecture. The device is implemented using a microcontroller core compatible with the Intel 80C32 ROMless
version of the 8051 architecture. The COM20051I is ideal for distributed control networking applications such as
those found in industrial/machine controls, building/factory automation, consumer products, instrumentation and
automobiles.
The COM20051I contains many features that are beneficial for embedded control applications. The microcontroller is
a fully-functional 16MHz 80C32 that is comparable to the Intel 80C32 with 2 timers. In contrast to other embedded
controller/networking solutions, the COM20051I adds a fully-featured, robust, powerful, and simple network interface
while retaining all of the basic 8051 peripherals, such as the serial port and counter/timers.
In addition, the COM20051I supports an Emulation Mode that permits the use of a standard 80C32 emulator in
conjunction with the COM20051I to develop software drivers for the network core. ARCNET core is mapped to a
256-byte page of the External Data Memory Space of the 80C32. This provides for an easy interface between the
CPU and the ARCNET core. The networking core is based around an ARCNET Token Bus protocol engine
that provides highly-reliable and fault tolerant message delivery at data rates ranging from 5Mbps down to 156
Kbps with message sizes varying from 0 to 507 bytes. The ARCNET protocol offers a simple, standardized, and
easily-understood networking solution for any application. The network interface supports several media interfaces,
including RS-485, coaxial, and twisted pair in either bus or star topologies. The network interface incorporates
powerful diagnostic features for network management and fault isolation. These include duplicate node ID detection,
reconfiguration detection, receive all (monitor) mode, receiver activity, and token detection.
ORDERING INFORMATION
Order Number: COM20051ILJ P
44 Pin PLCC Package
SMSC DS – COM20051I
Rev. 03/27/2000







COM20051I pdf, 数据表
BASIC ARCHITECTURE
The COM20051I consists of four functional blocks: the 80C32 microcontroller core, ARCNET network cell (includes
1K of buffer RAM), programmable address decoder, and programmable interrupt router. The internal architecture of
the COM20051I is shown in Figure 1.
The 80C32 microcontroller is a full ROMless implementation of the popular Intel 8051 series. The ARCNET network
core is similar in architecture to SMSC's popular COM20020 family of ARCNET controllers and retains the same
command and status flags of previous ARCNET controllers. The programmable address decoder maps the ARCNET
registers into a 256-byte page anywhere within the External Data Memory space of the 80C32. The ARCNET core
was mapped to the External Data Memory space to simplify software and application development and for
production test purposes. ARCNET core is available to the developer when working with the 8051 emulator. When
the COM20051I is put into Emulate mode, the internal microcontroller is put into a high impedance state, thus
allowing an external In-Circuit Emulator (ICE) to program the ARCNET core. The advantage of this approach versus
mapping the ARCNET registers into the internal memory (Special Function) area of the 80C32 is that dedicated
software development tools will not be necessary to debug application software. Since a majority of 8051
applications use only a small portion of the Data Memory space, there is no penalty paid for used address space.
There will also be no penalty in execution time, since cycle times for external data memory accesses and internal
direct memory moves are identical. The network interrupt can be routed to either of the two external interrupt ports or
can be assigned to one of the general purpose I/O ports. The ARCNET interrupt is internally wire ORed with the
external interrupt pin to allow greater system flexibility.
80C32 ARCHITECTURE AND INSTRUCTION SET
The 80C32 microcontroller core is identical to the 16MHz Intel 80C32 in all respects except for the absence of Timer
2. Please refer to the Intel Embedded Microcontrollers and Processors Databook, Volume 1, for details regarding
the 8051 architecture, peripherals, instruction set, and programming guide. Note that any access to the internal
ARCNET core or any external memorry access is visible on the pins of the COM20051I.
The following differences apply to the COM20051I:
1. Oscillator frequency is 40MHz instead of 16MHz. This is necessary to derive a 20MHz clock for the ARCNET
core. The processor still operates at 16MHz.
2. nEA pin - This pin must be tied to ground for normal internal processor operation. When tied to VCC, the
COM20051I will enter the Emulate mode.
3. Unused pins - The COM20051I is packaged in a 44-pin PLCC. Network I/O is generated on the four unused pins
of the standard 80C32 PLCC package. No DIP package is available.
4. Power Down operation - The Power Down mode can only be used in conjunction when the internal oscillator is
being used. If an external oscillator is used and the Power Down mode is invoked, damage may result to the
oscillator and to the COM20051I.
Clock Speed
The COM20051I processor operates at 16MHz and the network controller at a maximum 40MHz clock rate. A single
crystal oscillator is used to supply the two clocks: a 16MHz processor clock and a 20MHz network clock for the
nominal 2.5 Mbps data rate. Pins 20 and 21 are designated as crystal inputs. When clocking with an external
oscillator, pin 21 (XTAL1) functions as the clock input.
Emulate Mode
The COM20051I contains a unique feature called the Emulate mode that most 8051-based peripheral devices do
not accommodate. TheEmulate mode permits developers to access and program the internal ARCNET core using a
standard low-cost 8032 emulator. This feature eliminates the need for expensive dedicated development equipment
needed for other types of 8051-based peripheral devices. The Emulate mode is invoked by connecting the nEA pin
to VCC. This causes the internal 80C32 processor to enter a HI-Z state and changes the state of the COM20051I
pins according to the following table:
SMSC DS – COM20051I
Page 8
Rev. 03/27/2000







COM20051I equivalent, schematic
A transmission starts with an ALERT BURST consisting of 6 unit intervals of mark (logic "1"). Eight bit data
characters are then sent, with each character preceded by 2 unit intervals of mark and one unit interval of space.
Five types of transmission can be performed as described below:
Invitations To Transmit (ITT)
An Invitation To Transmit is used to pass the token from one node to another and is sent by the following sequence:
!"An ALERT BURST
!"An ITT (Invitation To Transmit: ASCII code 04H)
!"Two (repeated) DID (Destination ID) characters
ALERT
BURST
ITT DID DID
Free Buffer Enquiries (FBE)
A Free Buffer Enquiry is used to ask another node if it is able to accept a packet of data. It is sent by the following
sequence:
!"An ALERT BURST
!"An FBE - Free Buffer Enquiry: ASCII code 85H)
!"Two (repeated) DID (Destination ID) characters
ALERT
BURST
FBE DID DID
Data Packets (PAC)
A Data Packet consists of the actual data being sent to another node. It is sent by the following sequence:
!"An ALERT BURST
!"An PAC (Data Packet--ASCII code 01H)
!"An SID (Source ID) character
!"Two (repeated) DID (Destination ID) characters
!" A single COUNT character which is the 2's complement of the number of data bytes to follow if a short
packet is sent, or 00Hex followed by a COUNT character if a long packet is sent
!"N data bytes where COUNT = 256-N (or 512-N for a long packet)
!"Two CRC (Cyclic Redundancy Check) characters. The CRC polynomial used is: X16 + X15 + X2 + 1.
ALERT
PAC SID DID DID COUNT
BURST
data
data CRC CRC
Acknowledgements (ACK)
An Acknowledgement is used to acknowledge reception of a packet or as an affirmative response to FREE BUFFER
ENQUIRIES and is sent by the following sequence:
!" An ALERT BURST
!" An ACK (ACKnowledgement--ASCII code 86H) character
ALERT
BURST
ACK
SMSC DS – COM20051I
Page 16
Rev. 03/27/2000










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