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PDF ( 数据手册 , 数据表 ) ADF4360-1

零件编号 ADF4360-1
描述 Integrated Synthesizer and VCO
制造商 Analog Devices
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ADF4360-1 数据手册, 描述, 功能
Data Sheet
Integrated Synthesizer and VCO
ADF4360-1
FEATURES
GENERAL DESCRIPTION
Output frequency range: 2050 MHz to 2450 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4360-1 is a fully integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). The ADF4360-1 is
designed for a center frequency of 2250 MHz. In addition, there
is a divide-by-2 option available, whereby the user gets an RF
output of between 1025 MHz and 1225 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
CE RSET
REFIN
CLK
DATA
LE
ADF4360-1
14-BIT R
COUNTER
24-BIT
DATA REGISTER
24-BIT
FUNCTION
LATCH
LOCK
DETECT
MULTIPLEXER
MUTE
CHARGE
PUMP
PHASE
COMPARATOR
MUXOUT
CP
VVCO
VTUNE
CC
CN
INTEGER
REGISTER
PRESCALER
P/P+1
N = (BP + A)
13-BIT B
COUNTER
LOAD
LOAD
5-BIT A
COUNTER
VCO
CORE
DIVSEL = 1
OUTPUT
STAGE
RFOUTA
RFOUTB
÷2
AGND
DIVSEL = 2
DGND
CPGND
Figure 1.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-
sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







ADF4360-1 pdf, 数据表
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF4360-1
CPGND 1
AVDD 2
AGND 3
RFOUTA 4
RFOUTB 5
VVCO 6
ADF4360-1
TOP VIEW
(Not to Scale)
18 DATA
17 CLK
16 REFIN
15 DGND
14 CN
13 RSET
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
2 AVDD Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must have the same value as DVDD.
3, 8 to 11, 22 AGND
Analog Ground. This is the ground return path of the prescaler and VCO.
4
RFOUTA
VCO Output. The output level is programmable from −6 dBm to −13 dBm. See the Output Matching section
for a description of the various output stages.
5
RFOUTB
VCO Complementary Output. The output level is programmable from −6 dBm to −13 dBm. See the Output
Matching section for a description of the various output stages.
6 VVCO Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. VVCO must have the same value as AVDD.
7
VTUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
output voltage.
12 CC Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the
synthesizer. The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is
ICPmax
=
11.75
RSET
where RSET = 4.7 kΩ, ICPMAX = 2.5 mA.
14 CN Internal Compensation Node. This pin must be decoupled to VVCO with a 10 µF capacitor.
15
DGND
Digital Ground.
16
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
17 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
20 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
21
DVDD
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD must have the same value as AVDD.
23 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state
mode. Taking the pin high powers up the device depending on the status of the power-down bits.
24 CP Charge Pump Output. When enabled, this provides ± ICP to the external loop filter, which in turn drives the
internal VCO.
EP Exposed Pad. The exposed pad must be connected to AGND.
Rev. D | Page 7 of 24







ADF4360-1 equivalent, schematic
Data Sheet
ADF4360-1
Table 9. R Counter Latch
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSV RSV BSC2 BSC1 TMB LDP ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (1)
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
R14 R13
00
00
00
00
..
..
..
11
11
11
11
R12
0 ..........
0 ..........
0 ..........
0 ..........
. ..........
. ..........
. ..........
1 ..........
1 ..........
1 ..........
1 ..........
LDP
0
1
ABP2
0
0
1
1
ABP1
0
1
0
1
ANTIBACKLASH PULSE WIDTH
3.0ns
1.3ns
6.0ns
3.0ns
LOCK DETECT PRECISION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
R3 R2 R1
0 00
0 01
0 10
0 11
. ..
. ..
. ..
1 00
1 01
1 10
1 11
DIVIDE RATIO
Not Allowed
1
2
3
.
.
.
16380
16381
16382
16383
BSC2
0
0
1
1
BSC1
0
1
0
1
BAND SELECT CLOCK DIVIDER
1
2
4
8
Rev. D | Page 15 of 24










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