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PDF ( 数据手册 , 数据表 ) T83C5102

零件编号 T83C5102
描述 (T83C5101x) 8-bit Low Pin Count Microcontrollers
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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T83C5102 数据手册, 描述, 功能
Features
80C51 Code Compatible
– 8051 Instruction Compatible
– 16 I/O + 2 Outputs in 24 Pin Packages
16 I/O + 6 Outputs in 28 Pin Packages
– Three 16-bit Timer/Counters
– 256 Bytes Scratchpad RAM
Program Memory
8 KB ROM T83C5102
16 KB ROM T83C5101
16 KB EPROM/OTP T87C5101
High-speed Architecture
40 MHz from 2.7 to 5.5V, Commercial or Industrial Temperature Range:
40 MHz with a 40 MHz Crystal In Std. Mode
40 MHz with a 20 MHz Crystal In X2 Mode
66 MHz from 4.5 to 5.5V, Commercial Temperature Range
40 MHz with a 40 MHz Crystal in Std. Mode
66 MHz with a 33 MHz Crystal in X2 Mode
Dual Data Pointer
On-chip eXpanded RAM (XRAM) (256 bytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Asynchronous Port Reset
Interrupt Structure with
6 Interrupt Sources,
4-Level Priority Interrupt System
Full-duplex Enhanced UART
Framing Error Detection
Automatic Address Recognition
Low EMI (no ALE)
Power Control Modes
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Idle Mode
Power-down Mode
Packages: SO24, DIL24, SSOP24, SO28
8-bit Low Pin
Count
Microcontrollers
T83C5101
T87C5101
T83C5102
Description
The T8xC5101/02 family is a high performance CMOS ROM, OTP, EPROM derivative
of the 80C51 CMOS single chip 8-bit microcontroller.
The T8xC5101/02 family is a low pin count device where only Port 1, port 3 and 2/6
bits of a new port 4 are outputted. This prevents any external access, like external pro-
gram memory access (fetch, MOVC) or external data memory (MOVX). The
T8xC5101/02 family retains all features of the 80C51 with extended capacity 8 KB
ROM (5102), 16 KB ROM (5101)/16 KB EPROM/OTP (5101), 256 bytes of internal
RAM, a 6-source, 4-level interrupt system, an on-chip oscillator and three
timer/counters.
In addition, the T8xC5101/02 family has an XRAM of 256 bytes, the X2 feature, a
more versatile serial channel that facilitates multiprocessor communication (EUART),
a dual data pointer and an improved timer 2. The fully static design of the
T8xC5101/02 family allows to reduce system power consumption by bringing the
clock frequency down to any value, even DC, without loss of data.
The T8xC5101/02 family has 2 software-selectable modes of reduced activity for fur-
ther reduction in power consumption. In idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In power-down mode the
RAM is saved and all other functions are inoperative.
Rev. 4233G–8051–03/03
1







T83C5102 pdf, 数据表
T8xC5101/02
Enhanced Features
X2 Feature
Description
In comparison to the original 80C52, the T8xC5101/02 implements some new features,
which are:
The X2 option.
The Dual Data Pointer.
The extended RAM.
The 4 level interrupt priority system.
Some enhanced features are also located in the UART and the timer 2.
The T8xC5101/02 core needs only 6 clock periods per machine cycle. This feature
called X2provides the following advantages:
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Save power consumption while keeping same CPU power (oscillator power saving).
Save power consumption by dividing dynamically operating frequency by 2 in
operating and idle modes.
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1 shows the clock generation block diagram. X2 bit is
validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD
mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock Generation Diagram
XTAL1
FXTAL
XTAL1:2
20
1
FOSC
state machine: 6 clock cycles.
CPU control
X2
CKCON reg
8 T8xC5101/02
4233G805103/03







T83C5102 equivalent, schematic
It is possible to use timer 2 as a baud rate generator and a clock generator simulta-
neously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
Figure 6. Clock-Out Mode C/T2 = 0
XTAL1
:2
(:1 in X2 mode)
TR2
T2CON reg
TL2 TH2
(8-bit) (8-bit)
OVERFLOW
T2
T2EX
Toggle
QD
EXEN2
T2CON reg
RCAP2L RCAP2H
(8-bit) (8-bit)
T2OE
T2MOD reg
EXF2
T2CON reg
TIMER 2
INTERRUPT
16 T8xC5101/02
4233G805103/03










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零件编号描述制造商
T83C5101(T83C5101x) 8-bit Low Pin Count MicrocontrollersATMEL Corporation
ATMEL Corporation
T83C5102(T83C5101x) 8-bit Low Pin Count MicrocontrollersATMEL Corporation
ATMEL Corporation

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