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零件编号 | DAC8822 | ||
描述 | Multiplying Digital-to-Analog Converter | ||
制造商 | Burr-Brown | ||
LOGO | |||
1 Page
BurrĆBrown Products
from Texas Instruments
DAC8822
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
16-Bit, Dual, Parallel Input, Multiplying
Digital-to-Analog Converter
FEATURES
• ±0.5LSB DNL
• ±1LSB INL
• Low Noise: 12nV/√Hz
• Low Power Operation:
IDD = 1µA per Channel at 2.7V
• 2mA Full-Scale Current, with VREF = 10V
• Settling Time: 0.5µs
• 16-Bit Monotonic
• 4-Quadrant Multiplying Reference Inputs
• Reference Bandwidth: 10MHz
• Reference Input: ±18V
• Reference Dynamics: –105 THD
• Midscale or Zero Scale Reset
• Analog Power Supply: +2.7V to +5.5V
• TSSOP-38 Package
• Industry-Standard Pin Configuration
• Pin-Compatible with the 14-Bit DAC8805
• Temperature Range: –40°C to +125°C
APPLICATIONS
• Automatic Test Equipment
• Instrumentation
• Digitally Controlled Calibration
• Industrial Control PLCs
DESCRIPTION
The DAC8822 dual, multiplying digital-to-analog
converter (DAC) is designed to operate from a single
2.7V to 5.5V supply.
The applied external reference input voltage VREF
determines the full-scale output current. An internal
feedback resistor (RFB) provides temperature
tracking for the full-scale output when combined with
an external, current-to-voltage (I/V) precision
amplifier.
A RSTSEL pin allows system reset assertion (RS) to
force all registers to zero code when RSTSEL = '0',
or to midscale code when RSTSEL = '1'. Additionally,
an internal power-on reset forces all registers to zero
or midscale code at power-up, depending on the
state of the RSTSEL pin.
A parallel interface offers high-speed
communications. The DAC8822 is packaged in a
space-saving TSSOP-38 package and has an
industry-standard pinout. The device is specified
fromwww.DataSheet4U.com –40°C to +125°C.
For a 14-bit, pin-compatible version, see the
DAC8805.
DGND VDD
R1A RCOMA VREFA ROFSA
RFBA
R1A
R2A
ROFSA RFBA
D0
D15
WR
A0
A1
RS
LDAC
RSTSEL
Parallel
Bus
Interface
Input A
Register
Input B
Register
Control
Logic
Power-On
Reset
DAC A
Register
DAC B
Register
R1B
R2B
DAC A
DAC B
ROFSB RFBB
IOUTA
AGNDA
IOUTB
AGNDB
R1B RCOMB VREFB ROFSB
RFBB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS: VDD = +5V
Channel A
www.ti.com
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8 TA = +25°C
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65535
Code
Figure 2.
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8 TA = -40°C
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65535
Code
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8 TA = +125°C
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65535
Code
Figure 6.
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8 TA = +25°C
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65535
Code
Figure 3.
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8 TA = -40°C
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65535
Code
Figure 5.
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
0.8 TA = +125°C
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65535
Code
Figure 7.
8 Submit Documentation Feedback
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
APPLICATION INFORMATION
www.ti.com
DIGITAL INTERFACE
The parallel bus interface of the DAC8822 is comprised of a 16-bit data bus D0—D15, address lines A0 and A1,
and a WR control signal. Timing and control functionality are shown in Figure 1, and described in Table 2 and
Table 3. The address lines must be set up and stable before the WR signal goes low, to prevent loading
improper data to an undesired input register.
Both channels of the DAC8822 can be simultaneously updated by control of the LDAC signal, as shown in
Figure 1. Reset control (RS) and reset select control (RSTSEL) signals are provided to allow user reset ability to
either zero scale or midscale codes of both the input and DAC registers.
STABILITY CIRCUIT
For a current-to-voltage (I/V) design, as shown in Figure 42, the DAC8822 current output (IOUT) and the
connection with the inverting node of the op amp should be as short as possible and laid out according to
correct printed circuit board (PCB) layout design. For each code change, there is an output step function. If the
gain bandwidth product (GBP) of the op amp is limited and parasitic capacitance is excessive at the inverting
node, then gain peaking is possible. Therefore, a compensation capacitor C1 (4pF to 20pF, typ) can be added to
the design for circuit stability, as shown in Figure 42.
VDD
U1
VDD ROFS RFB
VREF
VREF DAC8822 IOUTA/B
C1
U2
OPA277
VOUT
GND
Figure 42. Gain Peaking Prevention Circuit with Compensation Capacitor
16 Submit Documentation Feedback
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页数 | 21 页 | ||
下载 | [ DAC8822.PDF 数据手册 ] |
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