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PDF ( 数据手册 , 数据表 ) NB100LVEP17

零件编号 NB100LVEP17
描述 Quad Differential Driver/Receiver
制造商 ON Semiconductor
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NB100LVEP17 数据手册, 描述, 功能
NB100LVEP17
2.5V / 3.3V Quad Differential
Driver/Receiver
Description
The NB100LVEP17 is a 4-bit differential line receiver. The design
incorporates two stages of gain, internal to the device, making it an
excellent choice for use in high bandwidth amplifier applications.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device.
Features
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
250 ps Typical Propagation Delay
Low Profile QFN Package
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −2.375 V to −3.8 V
Q Output Will Default LOW with Inputs Open or at VEE
VBB Output
These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAMS*
TSSOP−20
DT SUFFIX
CASE 948E
N100
VP17
ALYWG
G
24 1
24 PIN QFN
MN SUFFIX
CASE 485L
24
1
N100
VP17
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 8
1
Publication Order Number:
NB100LVEP17/D







NB100LVEP17 pdf, 数据表
NB100LVEP17
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
Package
Shipping
NB100LVEP17DTG
NB100LVEP17DTR2G
TSSOP−20
(Pb−Free)
75 Units / Rail
2500 Tape & Reel
NB100LVEP17MNG
NB100LVEP17MNR2G
QFN−24
(Pb−Free)
92 Units / Rail
3000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D − ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
http://onsemi.com
8














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