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零件编号 | WM8216 | ||
描述 | 60MSPS 10-bit 2-channel CCD Digitiser | ||
制造商 | Wolfson Microelectronics | ||
LOGO | |||
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WM8216
60MSPS 10-bit 2-channel CCD Digitiser
DESCRIPTION
FEATURES
The WM8216 is a 10-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 60MSPS.
• 10-bit ADC
• 60MSPS conversion rate
• Low power – 330mW typical
• 3.3V single supply operation
The device includes two analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. The output from each of these
channels is time multiplexed into a single high-speed 10-bit
Analogue to Digital Converter. The digital output data is
available in 10-bit wide parallel format.
• Single or dual channel operation
• Correlated double sampling
• Programmable gain (9-bit resolution)
• Programmable offset adjust (8-bit resolution)
• Flexible clamp timing
• Programmable clamp voltage
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
• Internally generated voltage references
• 32-lead QFN package
signals or during Clamping to clamp CCD signals. An
• Serial control interface
external reference level may also be supplied. ADC
references are generated internally, ensuring optimum
APPLICATIONS
performance from the device.
Using an analogue supply voltage of 3.3V and a digital
interface supply of 3.3V, the WM8216 typically only
consumes 330mW
• Digital Copiers
• USB2.0 compatible scanners
• Multi-function peripherals
• High-speed CCD/CIS sensor interface
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Production Data, March 2007, Rev 4.0
Copyright ©2007 Wolfson Microelectronics plc.
WM8216
INPUT VIDEO SAMPLING
Production Data
tRSD
tRSFVSR
tMF1RS
tMRVSR
tMFVSF
tVSD
tVSFMR
tMCLKL
E
n-5
tMCLKH
O
n-4
E
Figure 1 Two-channel CDS Operation (CDS=1)
tPR2
tPER
O
n-3
E
tPD
OE
n-2
n-1
Input
Video
RSMP
VSMP
MCLK
Output
Data
OP[9:0]
tRSD
PIXEL n
tRSFVSR
tMRVSR
tVSD
tVSFMR
tMFVSF
tMCLKH
tMCLKL
n-8
tMF1RS
n-7
tPR1
tPER
n-6
tPD
n-5
Figure 2 One-channel CDS Operation (CDS=1)
Notes:
1. The relationship between input video signal and sample points is controlled by VSMP and RSMP.
2. When VSMP is high the input video signal is connected to the Video sampling capacitors.
3. When RSMP is high the input video signal is connected to the Reset sampling capacitors.
4. RSMP must not go high before the first falling edge of MCLK after VSMP goes low.
5. It is required that the falling edge of VSMP should occur before the rising edge of MCLK.
6. In 1-channel CDS mode it is not possible to have equally spaced Video and Reset sample points with a 45MHz
MCLK.
7. Non-CDS operation is also possible; RSMP is not required in this mode but can be used to control input clamping.
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PD Rev 4.0 March 2007
8
WM8216
8
7
6
5
4
3
2
1
0
0 128 256 384
Gain Code (PGA[8:0])
Figure 11 PGA Gain Characteristic
Production Data
3.5
Max i/p V oltage
LOWREFS=0
3
Max i/p V oltage
LOWREFS=1
2.5
2
1.5
1
0.5
0
512 0
128 256 384
Gain Code (PGA[8:0])
512
Figure 12 Peak Input Voltage to Match ADC Full-scale Range
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA can be offset to match the full-scale range of the differential ADC (2*[VRT-
VRB]).
For negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. This will give an output
code of 3FF (hex) from the WM8216 for zero input. If code zero is required for zero differential input
then the INVOP bit should be set.
For positive going input signals the black level should be offset to the bottom of the ADC range by
setting PGAFS[1:0]=11. This will give an output code of 000 (hex) from the WM8216 for zero input.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01. Zero differential
input voltage gives mid-range ADC output, 1FF (hex).
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PD Rev 4.0 March 2007
16
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页数 | 27 页 | ||
下载 | [ WM8216.PDF 数据手册 ] |
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