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PDF ( 数据手册 , 数据表 ) FIN3383

零件编号 FIN3383
描述 (FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
制造商 Fairchild Semiconductor
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FIN3383 数据手册, 描述, 功能
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October 2003
Revised April 2005
FIN3385 FIN3383
FIN3384 FIN3386
Low Voltage 28-Bit Flat Panel Display Link
Serializers/Deserializers
General Description
The FIN3385 and FIN3383 transform 28 bit wide parallel
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 28 bits of input LVTTL data are sampled and trans-
mitted.
The FIN3386 and FIN3384 receive and convert the 4/3
serial LVDS data streams back into 28/21 bits of LVTTL
data. Refer to Table 1 for a matrix summary of the Serializ-
ers and Deserializers available. For the FIN3385, at a
transmit clock frequency of 85MHz, 28 bits of LVTTL data
are transmitted at a rate of 595Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and cable
size problems associated with wide and high-speed TTL
interfaces.
Features
s Low power consumption
s 20 MHz to 85 MHz shift clock support
s r1V common-mode range around 1.2V
s Narrow bus reduces cable size and cost
s High throughput (up to 2.38 Gbps throughput)
s Internal PLL with no external component
s Compatible with TIA/EIA-644 specification
s Devices are offered 56-lead TSSOP packages
Ordering Code:
Order Number Package Number
Package Description
FIN3383MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3384MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3385MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3386MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Part
FIN3385
FIN3383
FIN3386
FIN3384
TABLE 1. Display Panel Link Serializers/Deserializers Chip Matrix
CLK Frequency
85
66
85
66
LVTTL IN
28
28
LVDS OUT
4
4
LVDS IN LVTTL OUT
4 28
4 28
Package
56 TSSOP
56 TSSOP
56 TSSOP
56 TSSOP
© 2005 Fairchild Semiconductor Corporation DS500864
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FIN3383 pdf, 数据表
Receiver DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16)
Symbol
Parameter
LVTTL/CMOS DC Characteristics
VIH Input High Voltage
VIL Input Low Voltage
VOH Output High Voltage
VOL Output Low Voltage
VIK Input Clamp Voltage
IIN Input Current
IOFF Input/Output Power Off Leakage Current
IOS Output Short Circuit Current
Receiver LVDS Input Characteristics
VTH
VTL
VICM
IIN
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Common Mode Range
Input Current
Receiver Supply Current
ICCWR
4:28 Receiver Power Supply Current
for Worst Case Pattern (With Load)
(Note 17)
ICCWR
3:21 Receiver Power Supply Current
for Worst Case Pattern (With Load)
(Note 17)
Test Conditions
Min Typ Max Units
IOH 0.4 mA
IOL 2mA
IIK 18 mA
VIN 0V to 4.6V
VCC 0V,
All LVTTL Inputs/Outputs 0V to 4.6V
VOUT 0V
2.0
GND
2.7
10.0
3.3
0.06
0.79
60.0
VCC
0.8
0.3
1.5
10.0
r10.0
120
Figure 2, Table 2
Figure 2, Table 2
Figure 2, Table 2
VIN 2.4V, VCC 3.6V or 0V
VIN 0V, VCC 3.6V or 0V
100
0.05
100
2.35
r10.0
r10.0
CL 8 pF,
See Figure 3
CL 8 pF,
See Figure 3
32.5 MHz
40.0 MHz
66.0 MHz
85.0 MHz
32.5 MHz
40.0 MHz
66.0 MHz
85.0 MHz
49.0
53.0
78.0
90.0
70.0
75.0
114
135
60.0
65.0
100
115
V
V
V
V
V
PA
PA
mA
mV
mV
V
PA
PA
mA
mA
ICCPDT Powered Down Supply Current
PwrDn 0.8V (RxOut stays LOW)
NA 55.0 PA
tRCOP
Receiver Clock Output (RxCLKOut) Period
11.76
T
50.0
tRCOL
RxCLKOut LOW Time
See Figure 8
4.0 5.0 6.0 ns
tRCOH
RxCLKOut HIGH Time
(f 85MHz)
4.5 5.0 6.5 ns
tRSRC
RxOut Valid Prior to RxCLKOut
(Rising Edge Strobe)
3.5
ns
tRHRC
RxOut Valid After RxCLKOut
3.5 ns
tROLH
Output Rise Time (20% to 80%)
CL 8 pF,
2.0 3.5
ns
tROHL
Output Fall Time (80% to 20%)
See Figure 4
1.8 3.5
ns
tRCCD
Receiver Clock Input to Clock Output Delay
See Figure 20, (Note 18)
TA 25qC and VCC 3.3V
3.5 5.0 7.5 ns
tRPDD
Receiver Power-Down Delay
See Figure 13
1.0 Ps
tRSPB0 Receiver Input Strobe Position of Bit 0
0.49
0.84
1.19
ns
tRSPB1 Receiver Input Strobe Position of Bit 1
2.17
2.52
2.87
ns
tRSPB2 Receiver Input Strobe Position of Bit 2
3.85
4.20
4.55
ns
tRSPB3 Receiver Input Strobe Position of Bit 3
See Figure 17 (f 85MHz)
5.53
5.88
6.23
ns
tRSPB4 Receiver Input Strobe Position of Bit 4
7.21
7.56
7.91
ns
tRSPB5 Receiver Input Strobe Position of Bit 5
8.89
9.24
9.59
ns
tRSPB6 Receiver Input Strobe Position of Bit 6
10.57 10.92 11.27
ns
tRSKM
RxIN Skew Margin
See Figure 17, (Note 19)
290
ps
tRPLLS Receiver Phase Lock Loop Set Time
See Figure 11
10.0
ms
Note 16: All Typical values are at TA 25qC and with VCC 3.3V. Positive current values refer to the current flowing into device and negative values means
current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except 'VOD and VOD).
Note 17: The power supply current for the receiver can be different with the number of active I/O channels.
Note 18: Total channel latency from Sewrializer to deserializer is (T  tTCCD). There is the clock period.
Note 19: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
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8







FIN3383 equivalent, schematic
AC Loading and Waveforms (Continued)
Note: tRSKM is the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference).
Note: The minimum and maximum pulse position values are based on the bit position of each of the 7 bits within the LVDS data stream across PVT
(Process, Voltage Supply, and Temperature).
FIGURE 18. Receiver LVDS Input Skew Margin
Note: Test setup used considers no requirement for separation of RMS and deterministic jitter. Other hardware setup such as Wavecrest boxes can be used
if no M1 software is available, but the test methodology in Figure 20 should be followed.
FIGURE 19. Transmitter Clock Out Jitter Measurement Setup
Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter r3ns (cycle-to-cycle) clock
input. The specific test methodology is as follows:
Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left 3ns and to the right 3ns when data is HIGH.
The r3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst
case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise
(VCC noise frequency 2 MHz).
FIGURE 20. Timing Diagram of Transmitter Clock Input with Jitter
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