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PDF ( 数据手册 , 数据表 ) FIN324C

零件编号 FIN324C
描述 24-Bit Ultra-Low Power Serializer Deserializer Supporting Single and Dual Displays
制造商 Fairchild Semiconductor
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FIN324C 数据手册, 描述, 功能
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March 2007
FIN324C
24-Bit Ultra-Low Power Serializer Deserializer
Supporting Single and Dual Displays
Features
ƒ Ultra-Low Operating Power: ~4mA at 5.44MHz
ƒ Supports Dual-Display Implementations with RGB
or Microcontroller Interface
ƒ No External Timing Reference Needed
ƒ SPI Mode Support
ƒ Single Device Operates as a Serializer or
Deserializer
ƒ Direct Support for Motorola®-Style R/W
Microcontroller Interface
ƒ Direct Support for Intel®-Style /WE, /RE
Microcontroller Interface
ƒ 15MHz Maximum Strobe Frequency
ƒ Utilizes Fairchild’s Proprietary CTL Serial I/O
Technology
ƒ Available in BGA and MLP packages
ƒ Wide Parallel Supply Voltage Range: 1.60 to 3.0V
ƒ Low Power Core Operation: VDDS/A=2.5 to 3.0V
ƒ Voltage Translation Capability Across Pair with No
External Components
ƒ High ESD protection: >14.5kV HBM
ƒ Power-Saving Burst-Mode Operation
Applications
ƒ Single or Dual 16/18-Bit RGB Cell Phone Displays
ƒ Single or Dual 16/18-Bit Cell Phone Displays with
Microcontroller Interface
ƒ Single or Dual Mobile Display at QVGA or HVGA
Resolution
Description
The FIN324C is a 24-bit serializer / deserializer with dual
strobe inputs. The device can be configured as a master
or slave device through the master/slave select pin
(M/S). This allows for the same device to be used as
either a serializer or deserializer, minimizing component
types in the system. The dual strobe inputs allow
implementation of dual-display systems with a single
pair of µSerDes. The FIN324C can accommodate RGB,
microcontroller, or SPI mode interfaces. Read and write
transactions are supported when operating with a
Motorola-style microcontroller interface for one or both
displays. Unlike other SerDes solutions, no external
timing reference is required for operation.
The FIN324C is designed for ultra-low power operation.
Reset (/RES) and standby (/STBY) signals put the
device in an ultra-low power state. In standby mode, the
outputs of the slave device maintain state, allowing the
system to resume operation from the last-known state.
The device utilizes Fairchild’s proprietary ultra-low power,
low-EMI Current Transfer Logic™ (CTL) technology. The
serial interface disables between transactions to minimize
EMI at the fundamental serial interface and to conserve
power. LV-CMOS parallel output buffers have been
implemented with slew rate control to adjust for capacitive
loading and to minimize EMI.
The serialization bit clock is generated internally to the
FIN324C. The minimum bit clock frequency is always
great enough to handle the maximum strobe frequency.
Related Application Notes
ƒ AN-5058 µSerDes™ Family Frequently Asked
Questions
ƒ AN-5061 µSerDes™ Layout Guidelines
ƒ AN-6047 FIN324C Reset and Standby
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
www.fairchildsemi.com







FIN324C pdf, 数据表
Master/Slave READ/WRITE transactions
During a write data transfer, DP[17:0], CNTL[5:0],
R/W, and CKSEL are serialized and transmitted by
the master to the slave. The slave receives the
signals, outputs the data and control signals, and
generates either a WCLK0 or WCLK1 pulse based on
the value of CKSEL. The CKSEL signal must remain
stable throughout the transaction.
Read transactions have two phases: The Read-
Control Phase, where CNTL[5:0], R/W, CKSEL are
transmitted to the deserializer; and the Read-Data
Phase, where the DP[17:0] signals of the slave are
read and transmitted back to the master device. The
slave device generates its own strobe signal for
latching in the data. Slave data must be valid prior to
the WCLKn signal going HIGH.
Master Serializer Operation (Read Control Phase)
When the R/W signal is asserted HIGH and the
STROBE signal transitions LOW, the Read-Control
Phase of the read cycle is initiated. The R/W signal
must not transition until the READ cycle completes.
For a READ transaction, only eight control signals are
captured. The 18 DP bits are ignored during the
READ operation. The following sequence must occur
for data to be serialized properly:
Microcontroller Read Sequence (Read-Control Phase):
1. Selects input strobe source (CKSEL= 0 or 1).
2. CPU sends signals (R/W=1, CKSEL, CNTL[5:0]).
3. STROBE Signal transitions LOW.
4. Captures control bits.
5. Device leaves burst standby mode.
6. Serializes and sends control bits.
7. Serializer turns around serial I/O waiting for data.
Slave Deserializer Operation (Read-Control Phase)
Microcontroller Read Sequence (Read-Control Phase):
1. Deserializer leaves burst standby mode.
2. Begins receiving valid serial stream.
3. Captures data from serial transfer.
4. Turns around serial I/O.
5. Internally decodes that this is a READ transaction
and the WCLK to use.
6. Outputs control signals, 3-state DP data bus.
7. Outputs falling edge of WCLK pulse.
Slave Serializer Read Operation (Read-Data Phase)
The slave serializer is enabled on the tail end of the
Read-Control Phase of operation. The operation of
the serializer is identical to the master serialization
except that the strobe signal is generated internally
and only the data bits DP[17:0] are captured.
Microcontroller Read Sequence (Read-Data Phase):
1. Display device outputs data onto DP bus on
falling edge of WCLK.
2. Captures parallel data on generated rising edge
of WCLK signal.
3. Serializes data stream.
4. DP signals are sent.
5. CNTL signals are sent as 0.
6. Turns serial I/O around, awaiting next
transaction.
Master Deserializer Read Operation (Read-Data Phase):
Initially the deserializer is in low-power operation. The
deserializer wakes up when it detects CKSO+ and
CKSO- transition from LOW to normal operating range.
Microcontroller Read Sequence (Read-Data Phase):
1. Master deserializer wakes up when the CKSI+
and CKSI- signals reach valid levels.
2. Begins receiving valid serial stream.
3. Outputs data DP[17:0].
4. Turns serial I/O around and goes to burst standby
mode.
5. Processor asserts rising edge of strobe signal to
capture data.
SPI WRITE transaction
SPI mode is activated by asserting the PAR/SPI signal
low on both the master and slave device. A SPI write is
only performed when CKSEL=0. During a SPI
transaction, SCLK must be connected to CNTL[5] and is
the strobe source for serialization. SDAT is assumed to
be on CNTL[4] and all of the remaining control signals
and STRB0 are serialized. STRB0 should be connected
to the SPI mode chip select.
On the rising edge of SCLK, all eight control signals
(CNTL[5:0], R/W, CKSEL) are captured and serialized.
The data signals are not sent. The /CS signal on STRB0 is
captured in bit position CNTL[5]. The deserializer captures
the serial stream and outputs it to the parallel port.
As shown in Table 2, SDAT and SCLK are output on
multiple pins. The DP[7] and DP[6] connections can be
used for displays with dual-mode operation and the data
pins are multiplexed with the SPI signals. CNTL[5] and
CNTL[4] signals can be used when the signals are not
multiplexed.
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
8
www.fairchildsemi.com







FIN324C equivalent, schematic
AC Data Latencies
Symbol
Parameter
Test Conditions
Typ.(13)
Max.
Units
tPD-WR0
tPD-WR1
tPD-RD
tPD-RDC
tPD-RDD
tPD-SPI
Write Latency
Write Latency
Total Read Latency
Read Control Latency
Read Data Latency
SPI Write Latency
WRITE Mode, CKSEL=0(11,12)
See Figure 15
WRITE Mode, CKSEL=1(11,12)
See Figure 15
READ Mode(11,14)
See Figure 17
READ Mode(11,15)
See Figure 17
READ Mode(11,16)
See Figure 17
SPI-WRITE Mode(11,17)
See Figure 16
147
111
340
276
84
115
ns
ns
480 ns
ns
ns
ns
Notes:
11. Minimum times occur with maximum oscillator frequency. Maximum times occur with minimum oscillator
frequency.
12. Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time
across the flex cable and I/O propagation delays.
13. Assumes propagation delay across the flex cable and through the I/Os of 20ns.
14. Total read latency tPD-RD is the sum of the Read-Control Phase latency (tPD-RDC) and the Read-Data Phase latency
(tPD-RDD). tPD-RD = tPD-RDC+ tPD-RDD.
15. Read-Control latency is the sum of the delay through the master serializer and slave deserializer, plus flex cable
flight times and I/O propagation delays.
16. Read Data latency is the sum of the delay through the slave serializer and master deserializer, plus flex cable
flight times and I/O propagation delays.
17. SPI–Write latency is the sum of the delay through the master serializer and slave deserializer, plus the flight time
across the flex cable and I/O propagation delays.
AC Oscillator Specifications
Symbol
fOSC
tOSC-STBY
tOSC-RES
Parameter
Serial Operating
Frequency
Oscillator Stabilization
Time After Standby
Oscillator Stabilization
Time After Reset
Test Conditions
VDDA=VDDS=2.75V
/RES=1, /STBY Transition
VDDA=VDDS=2.75V
/STBY=1, /RES Transition
Min.
240
Typ. Max. Units
275 310 MHz
15 30
µs
30 50
µs
© 2006 Fairchild Semiconductor Corporation
FIN324C Rev. 1.0.5
16
www.fairchildsemi.com










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