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PDF ( 数据手册 , 数据表 ) ZL49020

零件编号 ZL49020
描述 (ZL49010 - ZL49031) Wide Dynamic Range DTMF Receiver
制造商 Zarlink Semiconductor
LOGO Zarlink Semiconductor LOGO 


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ZL49020 数据手册, 描述, 功能
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ZL49010/1, ZL49020/1, ZL49030/1
Wide Dynamic Range DTMF Receiver
Data Sheet
Features
• Wide dynamic range (50dB) DTMF Receiver
• Call progress (CP) detection via cadence
indication
• 4-bit synchronous serial data output
• Software controlled guard time for ZL490x0
• Internal guard time circuitry for ZL490x1
• Powerdown option (ZL4901x & ZL4903x)
• 3.579MHz crystal or ceramic resonator (ZL4903x
and ZL4902x)
• External clock input (ZL4901x)
• Guarantees non-detection of spurious tones
Applications
• Integrated telephone answering machine
• End-to-end signalling
• Fax Machines
Description
The ZL490xx is a family of high performance DTMF
receivers which decode all 16 tone pairs into a 4-bit
binary code. These devices incorporate an AGC for
wide dynamic range and are suitable for end-to-end
signalling. The ZL490x0 provides an early steering
(ESt) logic output to indicate the detection of a DTMF
September 2003
Ordering Information
ZL49010DAA
ZL49011DAA
ZL49020DAA
ZL49021DAA
ZL49030DCA
ZL49030DCB
ZL49030DDA
ZL49030DDB
ZL49031DCA
ZL49031DCB
ZL49031DDA
ZL49031DDB
8 Pin PDIP Tubes
8 Pin PDIP Tubes
8 Pin PDIP Tubes
8 Pin PDIP Tubes
18 Pin SOIC Tubes
18 Pin SOIC Tape & Reel
20 Pin SSOP Tubes
20 Pin SSOP Tape & Reel
18 Pin SOIC Tubes
18 Pin SOIC Tape & Reel
20 Pin SSOP Tubes
20 Pin SSOP Tape & Reel
-40°C to +85°C
signal and requires external software guard time to
validate the DTMF digit. The ZL490x1, with preset
internal guard times, uses a delay steering (DStD)
logic output to indicate the detection of a valid DTMF
digit. The 4-bit DTMF binary digit can be clocked out
synchronously at the serial data (SD) output. The SD
pin is multiplexed with call progress detector output. In
the presence of supervisory tones, the call progress
1
PWDN
VDD
VSS
Voltage
Bias Circuit
AGC
Anti-
alias
Filter
Dial
Tone
Filter
2
OSC2
OSC1
(CLK)
Oscillator
and
Clock
Circuit
To All Chip Clocks
1. ZL49010/1 and ZL49030/1 only.
2. ZL49020/1 and ZL49030/1 only.
3. ZL490x1 only.
High
Group
Filter
Low
Group
Filter
Steering
Circuit
Digital
Detector
Algorithm
Code
Converter
and
Latch
Energy
Detection
Figure 1 - Functional Block Diagram
Digital
Guard
Time3
Parallel to
Serial
Converter
& Latch
Mux
ESt
or
DStD
ACK
SD
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.







ZL49020 pdf, 数据表
ZL49010/1, ZL49020/1, ZL49030/1
Data Sheet
AC Electrical Characteristics - voltages are with respect to VDD=5V±5%, VSS=0V and temperature -40 to +85°C unless
otherwise stated.
Characteristics
Sym Min TypMax Units Test Conditions*
1 Valid input signal level
(each tone of composite signal)
2 Positive twist accept
-50
2.45
0 dBm 1,2,3,5,6,12
775 mVRMS
8 dB 1,2,3,4,11,12,15
3 Negative twist accept
8 dB 1,2,3,4,11,12,15
4 Frequency deviation accept
±1.5%± 2Hz
1,2,3,5,12
5 Frequency deviation reject
±3.5%
1,2,3,5,12,15
6 Third tone tolerance
-16 dB 1,2,3,4,5,12
7 Noise tolerance
-12 dB 7,9,12
8 Dial tone tolerance
+15 dB 8,10,12
9 Supervisory tones detect level
(Total power)
-35
dBm 16
10 Supervisory tones reject level
-50 dBm 16
11 Energy detector attack time
12 Energy detector decay time
13a Powerdown time
13b Powerup time
tSA
1.0 6.5
ms 16
tSD 3
25 ms 16
10 ms IDDQ 100µA
30 ms ZL49010/ZL49030
50 ms ZL49011/ZL49031
Note 14
14 Tone present detect time (ESt
tDP
3
13 20
ms ZL490x0
logic output)
15 Tone absent detect time (ESt
logic output)
tDA
3 15 ms ZL490x0
16 Tone duration accept
(DStD logic output)
tREC
40 ms ZL490x1
17 Tone duration reject
(DStD logic output)
tREC
20
ms ZL490x1
18 Interdigit pause accept (DStD
logic output)
tID
40 ms ZL490x1
19 Interdigit pause reject (DStD logic tDO
output)
20
ms ZL490x1
20 Data shift rate 40-60% duty cycle fACK
21 Propagation delay
(ACK to Data Bit)
tPAD
1.0 3.0
100 140
MHz
ns
13,15
1MHz fACK,
13,15
22 Data hold time (ACK to SD)
tDH 30 50
ns 13,15
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing
* Test Conditions
1. dBm refers to a reference power of 1 mW delivered into a 600 ohms load.
2. Data sequence consists of all DTMF digits.
3. Tone on = 40 ms, tone off = 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by ±1.5%± 2 Hz.
7. Bandwidth limited (0-3 kHz) Gaussian noise.
8. Precise dial tone frequencies are 350 Hz and 440 Hz (± 2%).
9. Referenced to lowest level frequency component in DTMF signal.
10. Referenced to the minimum valid accept level.
11. Both tones must be within valid input signal range.
12. Internal guard time for ZL490x1 = 20ms.
13. Timing parameters are measured with 70pF load at SD output.
14. Time duration between PWDN pin changes from ‘1‘ to ‘0‘ and ESt/DStD becomes active.
15. Guaranteed by design and characterization. Not subject to production testing.
16. Value measured with an applied tone of 450 Hz.
8
Zarlink Semiconductor Inc.














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