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PDF ( 数据手册 , 数据表 ) ZL30122

零件编号 ZL30122
描述 SONET/SDH Low Jitter Line Card Synchronizer
制造商 Zarlink Semiconductor
LOGO Zarlink Semiconductor LOGO 


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ZL30122 数据手册, 描述, 功能
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ZL30122
SONET/SDH
Low Jitter Line Card Synchronizer
Data Sheet
A full Design Manual is available to qualified customers.
To register, please send an email to
Features
• Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-253-CORE and ITU-T
G.813
• Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
• Programmable output synthesizer generates clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Digital Phase Locked-Loop (DPLL) provides all the
features necessary for generating SONET/SDH
compliant clocks including automatic hitless
reference switching, automatic mode selection
(locked, free-run, holdover), and selectable loop
bandwidth
Ordering Information
May 2006
ZL30122GGG 64 Pin CABGA
Trays
ZL30122GGG2 64 Pin CABGA* Trays
*Pb Free Tin/Silver/Copper
-40oC to +85oC
• Provides 3 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Provides 3 sync inputs for output frame pulse
alignment
• Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
• Configurable input to output delay, and output to
output phase alignment
• Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan
osco
osci
trst_b tck tdi tms tdo
Master
Clock
IEEE 1449.1
JTAG
ref0 ref2:0
ref1
ref2
sync0
sync1
sync2
sync2:0
Reference ref_&_sync_status
Monitors
dpll_lock dpll_holdover
diff_en
ref
DPLL
sync
SONET/SDH
APLL
Programmable
Synthesizer
diff_clk_p/n
sdh_clk
sdh_fp
p_clk
p_fp
int_b
SPI Interface
Controller &
State Machine
sck si so cs_b
rst_b
dpll_mod_sel
sdh_filter filter_ref0 filter_ref1
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.







ZL30122 pdf, 数据表
ZL30122
Data Sheet
Pin #
H5
Name
osco
Miscellaneous
F5 IC
H6 IC
H7 NC
H2 IC
Power and Ground
C3 VDD
C8
E8
F6
F8
G6
H8
E6 VCORE
F3
B7 AVDD
C4
B6 AVCORE
C7
F1
D3 VSS
D4
D5
D6
E3
E4
E5
E7
F4
F7
A6 AVSS
A8
C6
G1
I/O
Type
Description
O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected
when the osci pin is connected to a clock oscillator.
Internal Connection. Leave unconnected.
Internal Connection. Connect to ground.
No Connection. Leave unconnected.
Internal Connection. Connect to ground.
P Positive Supply Voltage. +3.3VDC nominal.
P
P
P
P
P
P
P Positive Supply Voltage. +1.8VDC nominal.
P
P Positive Analog Supply Voltage. +3.3VDC nominal.
P
P Positive Analog Supply Voltage. +1.8VDC nominal.
P
P
G Ground. 0 Volts.
G
G
G
G
G
G
G
G
G
G Analog Ground. 0 Volts.
G
G
G
I - Input
Id - Input, Internally pulled down
Iu - Input, Internally pulled up
O - Output
A - Analog
P - Power
G - Ground
8
Zarlink Semiconductor Inc.







ZL30122 equivalent, schematic
ZL30122
Data Sheet
2.0 Software Configuration
The ZL30122 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The
device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s
processor, or it can operate in a manual mode where the system processor controls most of the operation of the
device.
The following table provides a summary of the registers available for status updates and configuration of the device.
Addr
(Hex)
Register
Name
Reset
Value
(Hex)
Description
.
Type
00 id_reg
01 use_hw_ctrl
02 ref_fail_isr
03 dpll_isr
04 Reserved
05 ref_mon_fail_0
06 ref_mon_fail_1
07 Reserved
08 Reserved
09 ref_fail_isr_mask
0A dpll_isr_mask
0B Reserved
0C ref_mon_fail_mask_0
0D ref_mon_fail_mask_1
0E Reserved
0F Reserved
10 detected_ref_0
11 detected_ref_1
12 Reserved
13 Reserved
Miscellaneous Registers
A6 Chip and version identification and reset ready
indication register
00 Allows some functions of the device to be
controlled by hardware pins
Interrupts
FF Reference failure interrupt service register
70 DPLL interrupt service register
Leave as default
FF Ref0 and ref1 failure indications
FF Ref2 failure indication.
Leave as default
Leave as default
00 Reference failure interrupt service register
mask
00 DPLL interrupt service register mask
Leave as default
FF Control register to mask each failure indicator
for ref0 and ref1
FF Control register to mask failure indicator for
ref2
Leave as default
Leave as default
Reference Monitor Setup
FF Ref0 and ref1 auto-detected frequency value
status register
FF Ref2 auto-detected frequency value status
register
Leave as default
Leave as default
Table 5 - Register Map
R
R/W
R
StickR
StickR
StickR
R/W
R/W
R/W
R/W
R
R
R
R
16
Zarlink Semiconductor Inc.










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