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PDF ( 数据手册 , 数据表 ) ZL30111

零件编号 ZL30111
描述 POTS Line Card PLL
制造商 Zarlink Semiconductor
LOGO Zarlink Semiconductor LOGO 


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ZL30111 数据手册, 描述, 功能
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ZL30111
POTS Line Card PLL
Data Sheet
Features
January 2007
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
19.44 MHz input
• Provides a range of clock outputs: 2.048 MHz,
4.096 MHz and 8.192 MHz
• Provides 2 styles of 8 kHz framing pulses
• Automatic entry and exit from freerun mode on
reference fail
Ordering Information
ZL30111QDG
ZL30111QDG1
64 Pin TQFP Trays, Bake & Drypack
64 Pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Provides DPLL lock and reference fail indication
• Synchronizer for POTS line cards
• DPLL bandwidth of 922 Hz for all rates of input
reference and 58 Hz for an 8 kHz input reference
• Rate convert NTR 8kHz or GPON physical
interface clock to TDM clock
• Less than 0.6 nspp intrinsic jitter on all output clocks Description
• 20 MHz external master clock source: clock
oscillator or crystal
The ZL30111 POTS line card PLL contains a digital
• Simple hardware control interface
phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices.
The ZL30111 generates TDM clock and framing
signals that are phase locked to the input reference.
It helps ensure system reliability by monitoring its
reference for stability and by maintaining stable
output clocks during short periods when the
reference is unavailable.
REF
RST
OSCi
OSCo
REF_FAIL
LOCK
Reference
Monitor
State Machine
Master
Clock
Mode
Control
DPLL
C2o
C4
C8
F4
F8
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.







ZL30111 pdf, 数据表
ZL30111
Data Sheet
2.0 Functional Description
The ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices. Figure 1 is a functional block diagram which is described in the
following sections.
2.1 Reference Monitor
The input reference is monitored by two reference monitor blocks. The block diagram of reference monitoring is
shown in Figure 3. The reference frequency is detected and the clock is continuously monitored for two
independent criteria that indicate abnormal behavior of the reference signal, for example; loss of clock or excessive
level of frequency error. To ensure proper operation of the reference monitor circuit, the minimum input pulse
width restriction of 15 nsec must be observed.
Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference
clock is 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz and provides this information to the various monitor
circuits and the phase detector circuit of the DPLL.
Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of
approximately 30 µs to quickly detect large frequency changes.
Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase
hits or the complete loss of the clock.
REF
Reference Frequency
Detector
Coarse Frequency
Monitor
Single Cycle
Monitor
OR
REF_FAIL
Mode select
state machine
DPLL in FreeRun Mode
Figure 3 - Reference Monitor Circuit
Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single
cycle and coarse frequency failure flags force the DPLL into FreeRun mode.
8
Zarlink Semiconductor Inc.







ZL30111 equivalent, schematic
ZL30111
Data Sheet
DC Electrical Characteristics*
Characteristics
Sym.
Min.
Max. Units
Notes
1 Supply current with: OSCi = 0 V
IDDS
2 OSCi = Clock, OUT_SEL=0 IDD
4 Core supply current with: OSCi = 0 V ICORES
5 OSCi = Clock ICORE
6 Schmitt trigger Low to High
threshold point
Vt+
7 Schmitt trigger High to Low
threshold point
Vt-
8 Input leakage current
9 High-level output voltage
IIL
VOH
3.0
32
0
14
1.43
0.80
-105
2.4
6.5
47
22
20
1.85
1.10
105
mA
mA
µA
mA
V
V
µA
V
10 Low-level output voltage
VOL
0.4 V
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
* Voltages are with respect to ground (GND) unless otherwise stated.
outputs loaded
with 30 pF
All device inputs are
Schmitt trigger type.
VI = VDD or 0 V
IOH = 8 mA for clock and
frame-pulse outputs,
4 mA for status outputs
IOL = 8 mA for clock and
frame-pulse outputs,
4 mA for status outputs
AC Electrical Characteristics* - Timing Parameter Measurement Voltage Levels (see Figure 7)
Characteristics
Sym.
CMOS
Units
Notes
1 Threshold voltage
VT 0.5xVDD
2 Rise and fall threshold voltage high
VHM
0.7xVDD
3 Rise and fall threshold voltage low
VLM 0.3xVDD
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
* Voltages are with respect to ground (GND) unless otherwise stated.
V
V
V
ALL SIGNALS
tIF, tOF
Timing Reference Points
tIR, tOR
Figure 7 - Timing Parameter Measurement Voltage Levels
VVVHLTMM
16
Zarlink Semiconductor Inc.










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