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PDF ( 数据手册 , 数据表 ) ZL30102

零件编号 ZL30102
描述 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer
制造商 Zarlink Semiconductor
LOGO Zarlink Semiconductor LOGO 


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ZL30102 数据手册, 描述, 功能
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ZL30102
T1/E1 Stratum 4/4E Redundant System
Clock Synchronizer for DS1/E1 and H.110
Data Sheet
Features
• Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between an H.110 primary
master clock and a secondary master clock
• Supports Telcordia GR-1244-CORE Stratum 4 and
4E
• Supports ITU-T G.823 and G.824 for 2048 kbit/s
and 1544 kbit/s interfaces
• Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
• Simple hardware control interface
• Manual and Automatic hitless reference switching
between any combination of valid input reference
frequencies
• Accepts three input references and synchronizes
to any combination of 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz or 16.384 MHz inputs
• Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 3.088 MHz, 6.312 MHz, 16.384 MHz
and either 4.096 MHz and 8.192 MHz or
32.768 MHz and 65.536 MHz
• Provides 5 styles of 8 kHz framing pulses
• Holdover frequency accuracy of 1x10-7
November 2005
Ordering Information
ZL30102QDG 64 pin TQFP Trays, Bake & Drypack
ZL30102QDG1 64 pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
• Provides Lock, Holdover and selectable Out of
Range indication
• Attenuates wander from 1.8 Hz
• Less than 0.6 nspp intrinsic jitter on all output
clocks
• External master clock source: Clock Oscillator or
Crystal
Applications
• Synchronization and timing control for multi-trunk
DS1/ E1 terminal systems such as DSLAMs,
Gateways and PBXs
• Clock and frame pulse source for H.110 CT Bus,
ST-BUS, GCI and other time division multiplex
(TDM) buses
REF0
REF1
REF2
REF2_SYNC
REF_FAIL0
REF_FAIL1
REF_FAIL2
OOR_SEL
REF_SEL1:0
RST
OSCi OSCo TIE_CLR
FASTLOCK LOCK OUT_SEL
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Frequency
Select
MUX
DS1
Synthesizer
DS2
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C3o
C6o
TRST
MODE_SEL1:0 SEC_MSTR HMS HOLDOVER
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.







ZL30102 pdf, 数据表
ZL30102
Data Sheet
2.2 Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
Description
GND
Ground. 0 V
VCORE
LOCK
Positive Supply Voltage. +1.8 VDC nominal
Lock Indicator (Output). This output goes to a logic high when the PLL is frequency
locked to the selected input reference.
HOLDOVER Holdover (Output). This output goes to a logic high whenever the PLL goes into
holdover mode.
REF_FAIL0
Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0
reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that
it is exhibiting abrupt phase or frequency changes.
REF_FAIL1
Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1
reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that
it is exhibiting abrupt phase or frequency changes.
REF_FAIL2
Reference 2 Failure Indicator (Output). A logic high at this pin indicates that the REF2
reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that
it is exhibiting abrupt phase or frequency changes.
TDO
Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge
of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
TMS
Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP
controller. This pin is internally pulled up to VDD. If this pin is not used then it should be
left unconnected.
TRST
Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure that
the device is in the normal functional state. This pin is internally pulled up to VDD. If
this pin is not used then it should be connected to GND.
TCK
Test Clock (Input): Provides the clock to the JTAG test logic. If this pin is not used then it
should be pulled down to GND.
VCORE
GND
Positive Supply Voltage. +1.8 VDC nominal
Ground. 0 V
AVCORE
TDI
Positive Analog Supply Voltage. +1.8 VDC nominal
Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this
pin. This pin is internally pulled up to VDD. If this pin is not used then it should be left
unconnected.
HMS
Hitless Mode Switching (Input). The HMS input controls phase accumulation during the
transition from Holdover or Freerun mode to Normal mode on the same reference. A logic
low at this pin will cause the ZL30102 to maintain the delay stored in the TIE corrector
circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high
on this pin will cause the ZL30102 to measure a new delay for its TIE corrector circuit
thereby minimizing the output phase movement when it transitions from Holdover or
Freerun mode to Normal mode.
MODE_SEL0 Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode of
operation, see Table 4 on page 20.
MODE_SEL1 Mode Select 1 (Input). See MODE_SEL0 pin description.
8
Zarlink Semiconductor Inc.







ZL30102 equivalent, schematic
REF
Output
Clock
REF
Output
Clock
REF
Output
Clock
REF
Output
Clock
HMS = 0
Normal mode
ZL30102
REF
Output
Clock
Phase drift in Holdover mode
REF
Output
Clock
Return to Normal mode
REF
Output
Clock
TIE_CLR=0
REF
Output
Clock
HMS = 1
Normal mode
Data Sheet
Phase drift in Holdover mode
Return to Normal mode
TIE_CLR=0
Examples:
Figure 9 - Timing Diagram of Hitless Mode Switching
HMS=1: When ten Normal to Holdover to Normal mode transitions occur and in each case the Holdover mode was
entered for 2 seconds then the accumulated phase change (MTIE) could be as large as 2.13 µs.
- Phaseholdover_drift = 0.1 ppm x 2 s = 200 ns
- Phasemode_change = 0 ns + 13 ns = 13 ns
- Phase10 changes = 10 x (200 ns + 13 ns) = 2.13 µs
16
Zarlink Semiconductor Inc.










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