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PDF ( 数据手册 , 数据表 ) ST62T32B

零件编号 ST62T32B
描述 (ST62E32B / ST62T32B) 8-BIT OTP/EPROM MCUs
制造商 ST Microelectronics
LOGO ST Microelectronics LOGO 


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ST62T32B 数据手册, 描述, 功能
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ST62T32B
ST62E32B
8-BIT OTP/EPROM MCUs WITH A/D CONVERTER,
16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART
s 3.0 to 6.0V Supply Operating Range
s 8 MHz Maximum Clock Frequency
s -40 to +125°C Operating Temperature Range
s Run, Wait and Stop Modes
s 5 Interrupt Vectors
s Look-up Table capability in Program Memory
s Data Storage in Program Memory:
User selectable size
s Data RAM: 192 bytes
s Data EEPROM: 128 bytes
s User Programmable Options
s 30 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
s 9 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
s 8-bit Timer/ Counter with 7-bit programmable
prescaler
s 16-bit Auto-reload Timer with 7-bit
programmable prescaler (AR Timer)
s Digital Watchdog
s 8-bit A/D Converter with 21 analog inputs
s 8-bit Synchronous Peripheral Interface (SPI)
s 8-bit Asynchronous Peripheral Interface
(UART)
s On-chip Clock oscillator can be driven by Quartz
Crystal or Ceramic resonator
s Oscillator Safe Guard
s One external Non-Maskable Interrupt
s ST623x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port).
DEVICE SUMMARY
DEVICE
ST62T32B
ST62E32B
OTP
(Bytes)
7948
EPROM
(Bytes)
-
7948
I/O Pins
30
30
September 1998
PSDIP42
PQFP52
CDIP42W
(See end of Datasheet for Ordering Information)
Rev. 2.5
1/86
105







ST62T32B pdf, 数据表
ST62T32B ST62E32B
1.3 MEMORY MAP
1.3.1 Introduction
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Briefly, Program space contains user program
code in Program memory and user vectors; Data
space contains user data in RAM and in Program
memory, and Stack space accommodates six lev-
els of stack for subroutine and interrupt service
routine nesting.
1.3.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register).
Program Space is organised in four 2K pages.
Three of them are addressed in the 000h-7FFh lo-
cations of the Program Space by the Program
Counter and by writing the appropriate code in the
Program ROM Page Register (PRPR register). A
Figure 5. Memory Addressing Diagram
common (STATIC) 2K page is available all the
time for interrupt vectors and common subrou-
tines, independently of the PRPR register content.
This “STATIC” page is directly addressed in the
0800h-0FFFh by the MSB of the Program Counter
register PC 11. Note this page can also be ad-
dressed in the 000-7FFh range. It is two different
ways of addressing the same physical memory.
Jump from a dynamic page to another dynamic
page is achieved by jumping back to the static
page, changing contents of PRPR and then jump-
ing to the new dynamic page.
Figure 4. 8Kbytes Program Space Addressing
PC
SPACE 0000h
000h
7FFh
Page 0
800h
FFFh
Page 1
Static
Page
ROM SPACE
Page 1
Static
Page
Page 2
1FFFh
Page 3
PROGRAM SPACE
DATA SPACE
0000h
PROGRAM
MEMORY
0FF0h
0FFFh
INTERRUPT &
RESET VECTORS
0-63
000h
RAM / EEPROM
BANKING AREA
03Fh
040h
07Fh
080h
081h
082h
083h
084h
DATA READ-ONLY
MEMORY WINDOW
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
RAM
0C0h
0FFh
DATA READ-ONLY
MEMORY
WINDOW SELECT
DATA RAM
BANK SELECT
ACCUMULATOR
VR01568
8/86
112







ST62T32B equivalent, schematic
ST62T32B ST62E32B
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses. In-core communication is arranged as
shown in Figure 7; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip pe-
ripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
2.2 CPU REGISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic cal-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Figure 7. ST6 Core Block Diagram
Indirect Registers (X, Y). These two indirect reg-
isters are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be ad-
dressed in the data space as RAM locations at ad-
dresses 80h (X) and 81h (Y). They can also be ac-
cessed with the direct, short direct, or bit direct ad-
dressing modes. Accordingly, the ST6 instruction
set can use the indirect registers as any other reg-
ister of the data space.
Short Direct Registers (V, W). These two regis-
ters are used to save a byte in short direct ad-
dressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the di-
rect and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct regis-
ters as any other register of the data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an oper-
and, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
RESET
0,01 TO 8MHz
OSCin
OSCout
CONTROLLER
INTERR UPTS
DATA SPACE
OPCOD E
FLAG
VALUES
2
CONTROL
SIGNALS
ADDRESS /READ LINE
DATA
RAM/EEPROM
PRO GRAM
ROM/EPR OM
12
Program Counter
and
6 LAYER STACK
ADDRESS 256
DEC ODER
DATA
ROM/EPROM
A-DATA B-DATA
DED ICATIONS
ACCUMULATOR
F LAGS
ALU
RESULTS TO DATA SPACE (WRITE LINE)
VR01811
16/86
120










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