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PDF ( 数据手册 , 数据表 ) AD8112

零件编号 AD8112
描述 fully buffered crosspoint switch matrix that operates
制造商 Analog Devices
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AD8112 数据手册, 描述, 功能
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FEATURES
Low cost, 16 × 8, high speed, nonblocking switch array
Pin-compatible 16 × 16 version available (AD8113)
Serial or parallel programming of switch array
Serial data out allows daisy chaining control of multiple
16 × 8 arrays to create larger switch arrays
Output disable allows connection of multiple devices
without loading the output bus
Complete solution
Buffered inputs
8 output amplifiers
Operates on ±5 V or ±12 V supplies
Low supply current of 54 mA
Excellent audio performance VS = ±12 V
±10 V output swing
0.002% THD at 20 kHz maximum 20 V p-p (RL = 600 Ω)
Excellent video performance VS = ±5 V
0.1 dB gain flatness of 10 MHz
0.1% differential gain error (RL = 1 kΩ)
0.1° differential phase error (RL = 1 kΩ)
Excellent ac performance
−3 dB bandwidth 60 MHz
Low all-hostile crosstalk of −83 dB at 20 kHz
Reset pin allows disabling of all outputs (connected to a
capacitor to ground provides power-on reset capability)
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
CCTV surveillance/DVR
Analog/digital audio routers
Video routers (NTSC, PAL, S-Video, SECAM)
Multimedia systems
Video conferencing
GENERAL DESCRIPTION
The AD8112 is a low cost, fully buffered crosspoint switch matrix
that operates on ±12 V for audio applications and ±5 V for
video applications. It offers a −3 dB signal bandwidth greater
than 60 MHz and channel switch times of less than 60 ns with
0.1% settling for use in both analog and digital audio. The
AD8112 operated at 20 kHz has a crosstalk performance of
−83 dB and isolation of 90 dB. In addition, ground/power pins
surround all inputs and outputs to provide extra shielding for
operation in the most demanding audio routing applications.
With a differential gain and differential phase better than 0.1%
and 0.1°, respectively, and a 0.1 dB flatness output of up to 10 MHz,
the AD8112 is suitable for many video applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Audio/Video, 60 MHz, 16 × 8,
Gain of +2 Crosspoint Switch
AD8112
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
CLK
DATA IN
UPDATE
CE
RESET
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
40 40
PARALLEL LATCH
40
DECODE
8 × 5:16 DECODERS
NO
CONNECT
8
AD8112
OUTPUT
128 BUFFER
G = +2
A0
A1
A2
DATA
OUT
SWITCH
MATRIX
Figure 1.
The AD8112 includes eight independent output buffers that can
be placed into a disabled state for paralleling crosspoint outputs
so that off channel loading is minimized. The AD8112 has a gain
of +2. It operates on voltage supplies of ±5 V or ±12 V while
consuming only 34 mA or 31 mA of current, respectively. The
channel switching is performed via a serial digital control (which
can accommodate the daisy chaining of several devices) or via
a parallel control, allowing updating of an individual output
without reprogramming the entire array.
The AD8112 is packaged in a 100-lead LQFP and is available
over the commercial temperature range of 0°C to 70°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.







AD8112 pdf, 数据表
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AD8112
Table 7. Operation Truth Table
CE UPDATE CLK DATA IN
1X
XX
01
Data i
DATA OUT
X
Data i-80
RESET
X
1
SER/PAR
X
0
01
00
XX
D0 ... D4,
A0 ... A2
N/A in
Parallel
Mode
XX
X
XX
X
1
1
0
1
X
X
Operation/Comment
No change in logic.
The data on the serial DATA IN line is loaded into serial register.
The first bit clocked into the serial register appears at DATA OUT
80 clocks later.
The data on the parallel data lines, D0 to D4, is loaded into the
80-bit serial shift register location addressed by A0 to A2.
Data in the 80-bit shift register transfers into the parallel
latches that control the switch array. Latches are transparent.
Asynchronous operation. All outputs are disabled. Remainder
of logic is unchanged.
PARALLEL
DATA
(OUTPUT
ENABLE)
SER/PAR
D0
D1
D2
D3
D4
DATA IN
(SERIAL)
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
CLK
CE
UPDATE
OUT00 EN
OUT01 EN
OUT02 EN
OUT03 EN
A0 OUT04 EN
A1 OUT05 EN
A2 OUT06 EN
OUT07 EN
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
DATA OUT
RESET
(OUTPUT ENABLE)
LE D
OUT00
B0
Q
LE D
OUT00
B1
Q
LE D
OUT00
B2
Q
LE D
OUT00
B3
Q
LE D
OUT00
EN
CLR Q
LE D
OUT01
B0
Q
LE D
OUT06
EN
CLR Q
LE D
OUT07
B0
Q
LE D
OUT07
B1
Q
LE D
OUT07
B2
Q
LE D
OUT07
B3
Q
LE D
OUT07
EN
CLR Q
128
SWITCH MATRIX
DECODE
Figure 5. Logic Diagram
8
OUTPUT ENABLE
Rev. 0 | Page 8 of 28







AD8112 equivalent, schematic
AD8112
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500mV/DIV
100ns/DIV
Figure 36. Large-Signal Pulse Response, VS = ±5 V, RL = 150 Ω
UPDATE
2V/DIV
VOUT
INPUT 0
INPUT 1
100ns/DIV
Figure 37. Switching Time, VS = ±5 V, RL = 150 Ω
1V/DIV
UPDATE
20mV/DIV
OUTPUT
100ns/DIV
Figure 38. Switching Transient, VS = ±5 V, RL = 150 Ω
5V/DIV
100ns/DIV
Figure 39. Large-Signal Pulse Response, VS = ±12 V, RL = 600 Ω
2V/DIV
UPDATE
10V/DIV
INPUT 0
VOUT
INPUT 1
100ns/DIV
Figure 40. Switching Time, VS = ±12 V, RL = 600 Ω
1V/DIV
UPDATE
20mV/DIV
OUTPUT
100ns/DIV
Figure 41. Switching Transient, VS = ±12 V, RL = 600 Ω
Rev. 0 | Page 16 of 28










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