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PDF ( 数据手册 , 数据表 ) ZL30109

零件编号 ZL30109
描述 DS1/E1 System Synchronizer
制造商 Zarlink Semiconductor
LOGO Zarlink Semiconductor LOGO 


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ZL30109 数据手册, 描述, 功能
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ZL30109
DS1/E1 System Synchronizer with
19.44 MHz Output
Data Sheet
Features
October 2004
• Supports Telcordia GR-1244-CORE Stratum 4 and
Stratum 4E
Ordering Information
• Supports ITU-T G.823 and G.824 for 2048 kbit/s and
1544 kbit/s interfaces
ZL30109QDG 64 pin TQFP
• Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
-40°C to +85°C
• Simple hardware control interface
• Accepts two input references and synchronizes to
any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
• Provides a range of clock outputs: 1.544 MHz,
2.048 MHz, 16.384 MHz, 19.44 MHz and either
4.096 MHz and 8.192 MHz or 32.768 MHz and
65.536 MHz
• Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
• Holdover frequency accuracy of 1.5 x 10-7
• Less than 24 psrms intrinsic jitter on the
19.44 MHz output clock, compliant with OC-3 and
STM-1 jitter specifications
• Less than 0.6 nspp intrinsic jitter on all output
clocks
• External master clock source: clock oscillator or
crystal
Applications
• Synchronization and timing control for DSLAM,
Gateway and PBX systems that require Stratum
4/4E timing
• Lock, Holdover and selectable Out of Range
indication
• Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
• Line Card synchronization for SDH/PDH
applications
• Clock and frame pulse source for ST-BUS, GCI
and other time division multiplex (TDM) buses
REF0
REF1
REF_FAIL0
REF_FAIL1
OOR_SEL
REF_SEL
RST
OSCi OSCo TIE_CLR
BW_SEL LOCK OUT_SEL
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Feedback Frequency
Select
MUX
DS1
Synthesizer
SONET/SDH
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C19o
F2ko
TRST
MODE_SEL1:0 HMS HOLDOVER
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.







ZL30109 pdf, 数据表
ZL30109
Data Sheet
Pin Description (continued)
Pin #
39
Name
C19o
Description
Clock 19.44 MHz (Output). This output is used in SONET/SDH applications.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
40 AGND Analog Ground. 0 V
41 AGND Analog Ground. 0 V
42 C4/C65o Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at
2.048 Mbps, 4.096 Mbps or 65.536 MHz (ST-BUS 65.536 Mbps). The output frequency is
selected via the OUT_SEL pin.
43 C8/C32o Clock 8.192 MHz or 32.768 MHz (Output). This output is used for ST-BUS and GCI
operation at 8.192 Mbps or for operation with a 32.768 MHz clock. The output frequency
is selected via the OUT_SEL pin.
44
AVDD
Positive Analog Supply Voltage. +3.3 VDC nominal.
45
AVDD
Positive Analog Supply Voltage. +3.3 VDC nominal.
46 C2o Clock 2.048 MHz (Output). This output is used for standard E1 interface timing and for
ST-BUS operation at 2.048 Mbps.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
47
C16o
Clock 16.384 MHz (Output). This output is used for ST-BUS operation with a
16.384 MHz clock.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
48 F8/F32o Frame Pulse (Output). This is an 8 kHz 122 ns active high framing pulse (OUT_SEL=0)
or it is an 8 kHz 31 ns active high framing pulse (OUT_SEL=1), which marks the
beginning of a frame.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
49 F4/F65o Frame Pulse ST-BUS 2.048 Mbps or ST-BUS at 65.536 MHz clock (Output). This
output is an 8 kHz 244 ns active low framing pulse (OUT_SEL=0), which marks the
beginning of an ST-BUS frame. This is typically used for ST-BUS operation at
2.048 Mbps and 4.096 Mbps. Or this output is an 8 kHz 15 ns active low framing pulse
(OUT_SEL=1), typically used for ST-BUS operation with a clock rate of 65.536 MHz.
50
F16o
Frame Pulse ST-BUS 8.192 Mbps (Output). This is an 8 kHz 61 ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mbps.
51 AGND Analog Ground. 0 V
52 IC Internal Connection. Connect this pin to ground.
8
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ZL30109 equivalent, schematic
ZL30109
Data Sheet
In Normal mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in
Normal mode. The frequency in Holdover mode is calculated from frequency samples stored 26 ms to 52 ms before
the ZL30109 entered Holdover mode. This ensures that the coarse frequency monitor and the single cycle monitor
have time to disqualify a bad reference before it corrupts the holdover frequency.
In Freerun mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator - the lock detector monitors if the output value of the phase detector is within the
phase-lock-window for a certain time. The selected phase-lock-window guarantees the stable operation of the
LOCK pin with maximum network jitter and wander on the reference input. If the DPLL is locked and then goes into
Holdover mode (auto or manual), the LOCK pin will initially stay high for 1 s. If at that point the DPLL is still in
holdover mode, the LOCK pin will go low; subsequently the LOCK pin will not return high for at least the full
lock-time duration. In Freerun mode the LOCK pin will go low immediately.
2.5 Frequency Synthesizers
The output of the DCO is used by the frequency synthesizers to generate the C1.5o, C2o, C4o, C8o, C16o, C19o,
C32o and C65o clocks and the F4o, F8o, F16o, F32o, F65o and F2ko frame pulses which are synchronized to the
selected reference input (REF0 or REF1). The frequency synthesizers use digital techniques to generate output
clocks and advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs
have limited driving capability and should be buffered when driving high capacitance loads.
2.6 State Machine
As shown in Figure 1, the control state machine controls the TIE Corrector Circuit and the DPLL. The control of the
ZL30109 is based on the inputs MODE_SEL1:0, REF_SEL and HMS.
2.7 Master Clock
The ZL30109 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
3.0 Control and Modes of Operation
3.1 Out of Range Selection
The frequency out of range limits for the precise frequency monitoring in the reference monitors are selected by the
OOR_SEL pin, see Table 1.
OOR_SEL
0
1
Application
Applicable Standard
DS1
E1
ANSI T1.403
Telcordia GR-1244-CORE Stratum 4/4E
ITU-T G.703
ETSI ETS 300 011
Table 1 - Out of Range Limits Selection
Out Of Range Limits
64 - 83 ppm
100 - 130 ppm
16
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