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零件编号 | PZ3064 | ||
描述 | 64 macrocell CPLD | ||
制造商 | NXP Semiconductors | ||
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INTEGRATED CIRCUITS
PZ3064
64 macrocell CPLD
Product specification
IC27 Data Handbook
Philips
Semiconductors
1997 Mar 05
Philips Semiconductors
64 macrocell CPLD
Product specification
PZ3064
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ Tamb ≤ +70°C; 3.0V ≤ VDD ≤ 3.6V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
VIL Input voltage low
VDD = 3.0V
0.8 V
VIH Input voltage high
VDD = 3.6V
2.0
V
VI Input clamp voltage
VDD = 3.0V, IIN = –18mA
–1.2 V
VOL Output voltage low
VDD = 3.0V, IOL = 8mA
0.5 V
VOH Output voltage high
VDD = 3.0V, IOH = –8mA
2.4
V
II Input leakage current
VIN = 0 to VDD
–10 10
µA
IOZ 3-Stated output leakage current
VIN = 0 to VDD
–10 10
µA
IDDQ
Standby current
VDD = 3.6V, Tamb = 0°C
50 µA
IDDD1
Dynamic current
VDD = 3.6V, Tamb = 0°C @ 1MHz
VDD = 3.6V, Tamb = 0°C @ 50MHz
1 mA
40 mA
IOS Short circuit output current
1 pin at a time for no longer than 1 second
–5
–100
mA
CIN Input pin capacitance
Tamb = 25°C, f = 1MHz
8 pF
CCLK
Clock input capacitance
Tamb = 25°C, f = 1MHz
5 12 pF
CI/O I/O pin capacitance
Tamb = 25°C, f = 1MHz
10 pF
NOTE:
1. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded.
Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing.
AC ELECTRICAL CHARACTERISTICS1 FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ Tamb ≤ +70°C; 3.0V ≤ VDD ≤ 3.6V
SYMBOL
PARAMETER
–10
MIN. MAX.
tPD_PAL Propagation delay time, input (or feedback node) to output through PAL
tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA
tCO Clock to out delay time
tSU_PAL Setup time (from input or feedback node) through PAL
tSU_PLA Setup time (from input or feedback node) through PAL + PLA
tH Hold time
tCH Clock High time
tCL Clock Low time
tR Input Rise time
tF
fMAX1
fMAX2
fMAX3
Input Fall time
Maximum FF toggle rate2 (1/tCH + tCL)
Maximum internal frequency2 (1/tSUPAL + tCF)
Maximum external frequency2 (1/tSUPAL + tCO)
tBUF Output buffer delay time
tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL
tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL+PLA
tCF Clock to internal feedback node delay time
tINIT Delay from valid VDD to valid reset
tER Input to output disable3
tEA Input to output valid
tRP Input to register preset
tRR Input to register reset
NOTES:
1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5pF.
2 10
3 12.5
27
5.5
8
0
4
4
20
20
125
91
80
1.5
8.5
11
5.5
50
12.5
12.5
15
15
–12
MIN. MAX.
2 12
3 14.5
28
7
9.5
0
5
5
20
20
100
74
67
1.5
10.5
13
6.5
50
14
14
16
16
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
µs
ns
ns
ns
ns
1997 Mar 05
88
Philips Semiconductors
64 macrocell CPLD
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
Product specification
PZ3064
SOT188-3
1997 Mar 05
96
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页数 | 20 页 | ||
下载 | [ PZ3064.PDF 数据手册 ] |
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