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PDF ( 数据手册 , 数据表 ) PZ3032

零件编号 PZ3032
描述 32 macrocell CPLD
制造商 NXP Semiconductors
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PZ3032 数据手册, 描述, 功能
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INTEGRATED CIRCUITS
PZ3032
32 macrocell CPLD
Product specification
IC27 Data Handbook
Philips
Semiconductors
1997 Feb 20







PZ3032 pdf, 数据表
Philips Semiconductors
32 macrocell CPLD
Product specification
PZ3032
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C Tamb +70°C; 3.0V VDD 3.6V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
VIL Input voltage low
VDD = 3.0V
0.8 V
VIH Input voltage high
VDD = 3.6V
2.0
V
VI Input clamp voltage
VDD = 3.0V, IIN = –18mA
–1.2 V
VOL Output voltage low
VDD = 3.0V, IOL = 8mA
0.5 V
VOH Output voltage high
VDD = 3.0V, IOH = –8mA
2.4
V
IIL Input leakage current low
VDD = 3.6V (except CKO), VIN = 0V –10 10
µA
IIH Input leakage current high
VDD = 3.6V, VIN = 3.0V
–10 10
µA
IIL Clock input leakage current
VDD = 3.6V, VIN = 0.4V
–10 10
µA
IOZL 3-Stated output leakage current low
VDD = 3.6V, VIN = 0.4V
–10 10
µA
IOZH
3-Stated output leakage current high
VDD = 3.6V, VIN = 3.0V
–10 10
µA
IDDQ
Standby current
VDD = 3.6V, Tamb = 0°C
35 µA
IDDD1
Dynamic current
VDD = 3.6V, Tamb = 0°C @ 1MHz
VDD = 3.6V, Tamb = 0°C @ 50MHz
0.5 mA
18 mA
IOS Short circuit output current
1 pin at a time for no longer than 1 second
–5
–100
mA
CIN Input pin capacitance
Tamb = 25°C, f = 1MHz
8 pF
CCLK
Clock input capacitance
Tamb = 25°C, f = 1MHz
5 12 pF
CI/O I/O pin capacitance
Tamb = 25°C, f = 1MHz
10 pF
NOTE:
1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded.
Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing.
AC ELECTRICAL CHARACTERISTICS1 FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C Tamb +70°C; 3.0V VDD 3.6V
SYMBOL
PARAMETER
–8
MIN. MAX.
tPD_PAL Propagation delay time, input (or feedback node) to output through PAL
2
tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA
3
tCO Clock to out delay time
2
tSU_PAL Setup time (from input or feedback node) through PAL
6.5
tSU_PLA Setup time (from input or feedback node) through PAL + PLA
9
tH Hold time
tCH Clock High time
3
tCL Clock Low time
3
tR Input rise time
tF Input fall time
fMAX1
Maximum FF toggle rate2 (1/tCH + tCL)
167
fMAX2
Maximum internal frequency2 (1/tSUPAL + tCF)
83
fMAX3
Maximum external frequency2 (1/tSUPAL + tCO)
74
tBUF Output buffer delay time
tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL
tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL + PLA
tCF Clock to internal feedback node delay time
tINIT Delay from valid VDD to valid reset
tER Input to output disable3
tEA Input to output valid
tRP Input to register preset
tRR Input to register reset
NOTES:
1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output CL = 5pF.
8
10.5
7
0
20
20
1.5
6.5
9
5.5
50
15
15
16
19
–10
MIN. MAX.
2 10
3 13
29
8.5
11.5
0
4
4
20
20
125
63
57
1.5
8.5
11.5
7.5
50
17
17
18
21
–12
MIN. MAX.
2 12
3 15
2 11
10.5
13.5
0
5
5
20
20
100
50
47
1.5
10.5
13.5
9.5
50
19
19
20
23
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
µs
ns
ns
ns
ns
1997 Feb 20
8














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