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PDF ( 数据手册 , 数据表 ) ISL12029

零件编号 ISL12029
描述 Real Time Clock/Calendar
制造商 Intersil Corporation
LOGO Intersil Corporation LOGO 


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ISL12029 数据手册, 描述, 功能
ISL12029, ISL12029ANOc1NTo-8nOR8taE8RcD-CEItNaOCotTMOauErMMSRTMhESeeNIcELehDNtonEDriDcEwaDFlwOSRwRuE.ipPnNpLtEeoArWrsCt iCElD.ceMEonSEmtIeNDG/rTetNsaccStember 16, 2010
FN6206.10
Real Time Clock/Calendar with I2C Bus™
and EEPROM
The ISL12029 device is a low power real time clock with
clock/calendar, power-fail indicator, clock output and crystal
compensation, two periodic or polled alarms (open drain
output), intelligent battery backup switching, CPU
Supervisor, integrated 512x8-bit EEPROM configured in 16
bytes per page.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
The ISL12029 and ISL12029A Power Control Settings are
different. The ISL12029 uses the Legacy Mode Setting, and
the ISL12029A uses the Standard Mode Setting.
Applications that have VBAT > VDD will require only the
ISL12029A. Please refer to “Power Control Operation” on
page 14 for more details. Also, please refer to “I2C
Communications During Battery Backup” on page 24 for
important details.
Pinout
ISL12029, ISL12029A
(14 LD TSSOP, SOIC)
TOP VIEW
X1
X2
NC
NC
NC
RESET
GND
1
2
3
4
5
6
7
14 VDD
13 VBAT
12 IRQ/FOUT
11 NC
10 NC
9 SCL
8 SDA
NC = No internal connection
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
- 3 Selectable Frequency Outputs
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day or Month
- Repeat Mode (periodic interrupts)
• Automatic Backup to Battery or SuperCap
- Power Failure Detection
- 800nA Battery Supply Current
• On-Chip Oscillator Compensation:
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512x8 Bits of EEPROM
- 16-Byte Page Write Mode (32 total pages)
- 8 Modes of BlockLock™ Protection
- Single Byte Write Capability
- Data Retention: 50 years
- Endurance: >2,000,000 Cycles Per Byte
• CPU Supervisor Functions
- Power-On Reset, Low Voltage Sense
- Watchdog Timer (0.25s, 0.75s, 1.5s)
• I2C Interface
- 400kHz Data Transfer Rate
• 14 Ld SOIC and 14 Ld TSSOP Packages
• Pb-Free (RoHS Compliant)
Applications
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/AutomotivePAR
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
I2C Bus™ is a trademark owned by NXP Semiconductors Netherlands, B.V.
BlockLock™ is a trademark of Intersil Corporation or one of its subsidiaries. Copyright Intersil Americas Inc. 2005, 2006, 2008, 2010.
All Rights Reserved. All other trademarks mentioned are the property of their respective owners.







ISL12029 pdf, 数据表
ISL12029, ISL12029A
Typical Performance Curves Temperature is +25°C unless otherwise specified
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.8
BSW = 0 OR 1
SCL, SDA PULL-UPS = 0V
SCL, SDA PULL-UPS = VBAT
BSW = 0 OR 1
2.3 2.8 3.3 3.8 4.3 4.8
VBAT (V)
FIGURE 5. IBAT vs VBAT, SBIB = 0
5.3
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1.8
SCL, SDA PULL-UPS = 0V
BSW = 0 OR 1
2.3 2.8 3.3 3.8 4.3 4.8
VBAT(V)
FIGURE 6. IBAT vs VBAT, SBIB = 1
5.3
5.0
4.5
4.0 VDD = 5.5V
3.5
3.0 VDD = 3.3V
2.5
2.0
1.5
1.0
0.5
0.0
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85
TEMPERATURE (°C)
FIGURE 7. IDD3 vs TEMPERATURE
1.4
1.2
VBAT = 3.0V
1.0
0.8
0.6
0.4
0.2
0.0
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85
TEMPERATURE (°C)
FIGURE 8. IBAT vs TEMPERATURE
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
VDD (V)
FIGURE 9. IDD3 vs VDD
8
80
60
40
20
0
-20
-40
-32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24 28
ATR SETTING
FIGURE 10. FOUT vs ATR SETTING
FN6206.10
December 16, 2010







ISL12029 equivalent, schematic
ISL12029, ISL12029A
overlapping to the following Alarm's Seconds register is
advised.
2. Other non-volatile writes: It is possible to do writes of
less than an entire page, but the final byte must always
be addresses 0000h through 0004h or 0008h though
000Ch to trigger a non-volatile write. Writing to those
blocks of 5 bytes sequentially, or individually, will trigger a
non-volatile write. If the DWA0 or DWA1 registers need to
be set, then enough bytes will need to be written to
overlap with the other Alarm register and trigger the
non-volatile write. For Example, if the DWA0 register is
being set, then the code can start with a multiple byte
write beginning at address 0006h, and then write 3 bytes
ending with the SCA1 register as follows:
Addr Name
0006h DWA0
0007h Y2K0
0008h SCA1
If the Alarm1 is used, SCA1 would need to have the correct
data written.
Power Control Operation
The power control circuit accepts a VDD and a VBAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
an Intersil RTC device for up to 10 years. Another option is
to use a SuperCap for applications where VDD is interrupted
for up to a month. See “Application Section” on page 23 for
more information.
There are two options for setting the change-over conditions
from VDD to Battery back-up mode. The BSW bit in the PWR
register controls this operation.
Option 1 - Standard Mode (Default for ISL12029A)
Option 2 - Legacy Mode (Default for ISL12029)
TABLE 7. VBAT TRIP POINT WITH DIFFERENT BSW SETTING
VBAT TRIP POINT
BSW BIT
(V) POWER CONTROL SETTING
0 2.2 Standard Mode (ISL12029A)
1
VDD < VBAT
Legacy Mode (ISL12029)
Note that applications that have VBAT > VDD will require the
ISL12029A (standard mode) for proper startup. Note that the
I2C bus may or may not be operational during battery
backup, that function is controlled by the SBIB bit. That
operation is covered after the power control section.
OPTION 1 - STANDARD POWER CONTROL MODE
(DEFAULT FOR ISL12029A)
In the Standard mode, the supply will switch over to the
battery when VDD drops below VTRIP or VBAT, whichever is
lower. In this mode, accidental operation from the battery is
prevented since the battery backup input will only be used
when the VDD supply is shut off.
To select Option 1, BSW bit in the Power Register must be
set to “BSW = 0”. A description of power switchover follows.
Standard Mode Power Switchover
• Normal Operating Mode (VDD) to Battery Backup Mode
(VBAT)
To transition from the VDD to VBAT mode, both of the
following conditions must be met:
- Condition 1:
VDD < VBAT - VBATHYS
where VBATHYS 50mV
- Condition 2:
VDD < VTRIP
where VTRIP 2.2V
• Battery Backup Mode (VBAT) to Normal Mode (VDD)
The ISL12029 device will switch from the VBAT to VDD mode
when one of the following conditions occurs:
- Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS 50mV
- Condition 2:
VDD > VTRIP + VTRIPHYS
where VTRIPHYS 30mV
There are two discrete situations that are possible when using
Standard Mode: VBAT < VTRIP and VBAT > VTRIP. These two
power control situations are illustrated in Figures 13 and 14.
BATTERY
VDD
BACKUP
MODE
VTRIP
VBAT
2.2V
1.8V
VBAT - VBATHYS
VBAT + VBATHYS
FIGURE 13. BATTERY SWITCHOVER WHEN VBAT < VTRIP
VDD
VBAT
VTRIP
VTRIP
BATTERY BACKUP
MODE
3.0V
2.2V
VTRIP + VTRIPHYS
FIGURE 14. BATTERY SWITCHOVER WHEN VBAT > VTRIP
16 FN6206.10
December 16, 2010










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