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PDF ( 数据手册 , 数据表 ) C9812

零件编号 C9812
描述 Low EMI Clock Generator
制造商 Cypress Semiconductor
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C9812 数据手册, 描述, 功能
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APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel810E Chipset Systems
Product Features
Intel’s 810E clock solution
3 copies of CPU Clock (CPU[0:1] and CPU_ITP)
9 copies of SDRAM Clock (SDRAM[0:7] and DCLK)
8 copies of PCI Clock
2 copies of 3V66 Clock
2 copies of APIC Clock, synchronous to PCI Clock
1 REF Clock
1 USB Clock (Non SSC)
1 DOT Clock (Non SSC)
Power Down Feature
Spread Spectrum Support
SMBUS Support for turning off unused clocks
Block Diagram
Frequency Table (MHz)
SEL2 SEL1 SEL0 CPU SDRAM
PCI
X 0 0 Tristate Tristate Tristate
X01
Test mode (see table2)
0 1 0 66.6 100
33.3
0 1 1 100 100
33.3
1
1
X 133.3
100
33.3
Table 1
Note: The following clocks remain fixed frequencies
except in Test Mode.
3V66=66.6MHz, USB/DOT=48MHz, REF=14.318MHz
and IOAPIC=33.3MHz.
Pin Configuration
XIN
XOUT
36pF
300K
36pF
SCLK
SDATA
s2
Rin
i2c-clk
i2c-data
ioapic
cpu
SEL1
SEL0
PD#
VDD
VDD
s1
sdram
s0
pwr_dwn#
66m
PLL1
Rin
pci
48
PD#
i2c-clk
i2c-data
PLL2
Fig.1
VDD
1
REF / SEL2
VDDI
2 IOAPIC(0:1)
VDDC
3 CPU(0:2)
VDDS
9 SDRAM(0:7), DCLK
VDD
2 3V66(0:1)
VDD
8 PCI(0:7)
VDD
1 DOT
VDD
1 USB
SEL2/REF
VDD
XIN
XOUT
VSS
VSS
3V660
3V661
VDD
VDD
PCI0_ICH
PCI1
PCI2
VSS
PCI3
PCI4
VSS
PCI5
PCI6
PCI7
VDD
VDDA
VSSA
VSS
USB
DOT
VDD
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VSS
55 IOAPIC0
54 IOAPIC1
53 VDDI
52 CPU0
51 VDDC
50 CPU1
49 CPU2_ITP
48 VSS
47 VSS
C
46
45
SDRAM0
SDRAM1
9 44 VDDS
8 43 SDRAM2
1
42
41
SDRAM3
VSS
2 40 SDRAM4
39 SDRAM5
38 VDDS
37 SDRAM6
36 SDRAM7
35 VSS
34 DCLK
33 VDD
32 PD#
31 SCLK
30 SDATA
29 SEL1
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 1 of 18







C9812 pdf, 数据表
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel810E Chipset Systems
SDATA IS OUTPUT PIN
ACK
ACK
SDATA IS INPUT PIN
1
1
0
1
0
0
1
0
COMMAND BYTE
(DON'TCARE)
SDATA
MSB
LSB
SCLK
START CONDITION
COUNT BYTE
(DON'TCARE)
ACK
BYTE 0
(VALID DATA)
ACK
8
BYTE N (LAST
VALID DATA)
ACK
CONTINUED
CONTINUED
88
8
Figure 7
SMBUS Communications Waveforms
STOP CONDITION
Test and Measurement Condition
3.3V signals
tDC
-
3.3V
2.4V
1.5V
Output under Test
Probe
Load Cap
-
2.0V
1.25V
2.5V signals
tDC
-
2.5V
-
0.4V
0.4V
0V
0V
Tr Tf
Tr Tf
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Fig.8
Document#: 38-07053 Rev. **
05/03/01
Page 8 of 18







C9812 equivalent, schematic
APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel810E Chipset Systems
Package Drawing and Dimensions
EH
C
L
D
B
A2
A1
e
a
A
56 Pin SSOP Outline Dimensions
INCHES
MILLIMETERS
SYMBOL MIN
NOM MAX
MIN NOM MAX
A 0.095 0.102 0.110 2.41 2.59 2.79
A1 0.008 0.012 0.016 0.20 0.31 0.41
A2 0.088 0.090 0.092 2.24 2.29 2.34
B 0.008 0.010 0.0135 0.203 0.254 0.343
C 0.005 - 0.010 0.127 - 0.254
D .720 .725 .730 18.29 18.42 18.54
E 0.292 0.296 0.299 7.42 7.52 7.59
e 0.025 BSC
0.635 BSC
H 0.400 0.406 0.410 10.16 10.31 10.41
L 0.024 0.032 0.040 0.61 0.81 1.02
a 0º
5º 8º
0º 5º 8º
X 0.085 0.093 0.100 2.16 2.36 2.54
Ordering Information
Part Number
Package Type
C9812DYB
56 PIN SSOP
Marking: Example: Cypress
C9812
Date Code, Lot #
C9812DYB
Flow
B = Commercial, 0 to 70ºC
Package
Y = SSOP
Revision
Device Number
Production Flow
Commercial, 0 to 70ºC
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 16 of 18










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