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PDF ( 数据手册 , 数据表 ) AD9228

零件编号 AD9228
描述 Serial LVDS 1.8 V A/D Converter
制造商 Analog Devices
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AD9228 数据手册, 描述, 功能
Data Sheet
Quad, 12-Bit, 40/65 MSPS
Serial LVDS 1.8 V A/D Converter
AD9228
FEATURES
4 ADCs integrated into 1 package
119 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
ENOB = 11.3 bits
SFDR = 82 dBc (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
315 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital con-
verter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 65 MSPS and is optimized for
outstanding dynamic performance and low power in applications
where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD DRGND
VIN + A
VIN – A
VIN + B
VIN – B
VIN + C
VIN – C
VIN + D
VIN – D
VREF
SENSE
REFT
REFB
AD9228
12
PIPELINE
ADC
SERIAL
LVDS
12
PIPELINE
SERIAL
ADC
LVDS
12
PIPELINE
ADC
SERIAL
LVDS
12
PIPELINE
SERIAL
ADC
LVDS
REF
SELECT
+– 0.5V
SERIAL PORT
INTERFACE
DATA RATE
MULTIPLIER
D+A
D–A
D+B
D–B
D+C
D–C
D+D
D–D
FCO+
FCO–
DCO+
DCO–
RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK–
Figure 1.
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-
channel power-down is supported and typically consumes less
than 2 mW when all channels are disabled.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9228 is available in an RoHS compliant, 48-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package.
2. Low power of 119 mW/channel at 65 MSPS.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 390 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9259 (14-bit).
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.







AD9228 pdf, 数据表
Data Sheet
AD9228
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
CLOCK3
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
AD9228-40
Min Typ Max
40
10
12.5
12.5
2.0
2.0
(tSAMPLE/24) − 300
(tSAMPLE/24) − 300
2.7
300
300
2.7
tFCO +
(tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±50
3.5
3.5
(tSAMPLE/24) + 300
(tSAMPLE/24) + 300
±150
600
375
8
500
<1
1
AD9228-65
Min Typ Max
65
10
7.7
7.7
2.0
2.0
(tSAMPLE/24) − 300
(tSAMPLE/24) − 300
2.7
300
300
2.7
tFCO +
(tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±50
3.5
3.5
(tSAMPLE/24) + 300
(tSAMPLE/24) + 300
±150
600
375
8
500
<1
2
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ns
μs
CLK
cycles
ps
ps rms
CLK
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
3 Can be adjusted via the SPI.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
Rev. E | Page 7 of 56







AD9228 equivalent, schematic
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
AIN = –0.5dBFS
SNR = 70.51dB
–20
ENOB = 11.42 BITS
SFDR = 86.00dBc
–40
–60
–80
–100
–120
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 15. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 40 MSPS
AD9228
0
AIN = –0.5dBFS
SNR = 69.62dB
–20
ENOB = 11.27 BITS
SFDR = 72.48dBc
–40
–60
–80
–100
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
Figure 18. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 65 MSPS
0
AIN = –0.5dBFS
SNR = 70.38dB
–20 ENOB = 11.40 BITS
SFDR = 81.13dBc
–40
–60
–80
–100
–120
0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz)
Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 40 MSPS
0
AIN = –0.5dBFS
SNR = 68.74dB
–20
ENOB = 11.12 BITS
SFDR = 72.99dBc
–40
–60
–80
–100
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
Figure 19. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS
0
AIN = –0.5dBFS
SNR = 70.53dB
–20
ENOB = 11.42 BITS
SFDR = 86.04dBc
–40
–60
–80
–100
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
Figure 17. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 65 MSPS
0
AIN = –0.5dBFS
SNR = 67.68dB
–20
ENOB = 10.95 BITS
SFDR = 62.23dBc
–40
–60
–80
–100
–120
0
5 10 15 20 25 30
FREQUENCY (MHz)
Figure 20. Single-Tone 32k FFT with fIN = 170 MHz, fSAMPLE = 65 MSPS
Rev. E | Page 15 of 56










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