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PDF ( 数据手册 , 数据表 ) AD7328

零件编号 AD7328
描述 12-Bit Plus Sign ADC
制造商 Analog Devices
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AD7328 数据手册, 描述, 功能
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8-Channel, Software-Selectable True
Bipolar Input, 12-Bit Plus Sign ADC
AD7328
FEATURES
12-bit plus sign SAR ADC
True bipolar input ranges
Software-selectable input ranges
±10 V, ±5 V, ±2.5 V, 0 V to +10 V
1 MSPS throughput rate
Eight analog input channels with channel sequencer
Single-ended, true differential, and pseudo differential
analog input capability
High analog input impedance
Low power: 21 mW
Temperature indicator
Full power signal bandwidth: 22 MHz
Internal 2.5 V reference
High speed serial interface
Power-down modes
20-lead TSSOP package
iCMOSprocess technology
GENERAL DESCRIPTION
The AD73281 is an 8-channel, 12-bit plus sign, successive
approximation ADC designed on the iCMOS (industrial
CMOS) process. iCMOS is a process combining high voltage
silicon with submicron CMOS and complementary bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage parts could achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can accept bipolar input signals while providing
increased performance, dramatically reduced power consumption,
and reduced package size.
The AD7328 can accept true bipolar analog input signals. The
AD7328 has four software-selectable input ranges, ±10 V, ±5 V,
±2.5 V, and 0 V to +10 V. Each analog input channel can be
independently programmed to one of the four input ranges. The
analog input channels on the AD7328 can be programmed to be
single-ended, true differential, or pseudo differential.
The ADC contains a 2.5 V internal reference. The AD7328 also
allows for external reference operation. If a 3 V reference is applied
to the REFIN/OUT pin, the AD7328 can accept a true bipolar
±12 V analog input. Minimum ±12 V VDD and VSS supplies are
required for the ±12 V input range. The ADC has a high speed
serial interface that can operate at throughput rates up to 1 MSPS.
FUNCTIONAL BLOCK DIAGRAM
VDD
REFIN/OUT VCC
AD7328
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
I/P
MUX
CHANNEL
SEQUENCER
2.5V
VREF
T/H
13-BIT
SUCCESSIVE
APPROXIMATION
ADC
TEMPERATURE
INDICATOR
CONTROL LOGIC
AND REGISTERS
DOUT
SCLK
CS
DIN
AGND
VSS DGND
Figure 1.
VDRIVE
PRODUCT HIGHLIGHTS
1. The AD7328 can accept true bipolar analog input signals,
±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.
2. The eight analog inputs can be configured as eight single-
ended inputs, four true differential input pairs, four pseudo
differential inputs, or seven pseudo differential inputs.
3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-
compatible interface.
4. Low power, 30 mW, at a maximum throughput rate of
1 MSPS.
5. Channel sequencer.
Table 1. Similar Product Selection
Device Throughput
Number Rate
Number of Bits
AD7329 1000 kSPS
12-bit plus sign
AD7327 500 kSPS
12-bit plus sign
AD7324 1000 kSPS
12-bit plus sign
AD7323 500 kSPS
12-bit plus sign
AD7322 1000 kSPS
12-bit plus sign
AD7321 500 kSPS
12-bit plus sign
Number of
Channels
8
8
4
4
2
2
1 Protected by U.S. Patent No. 6,731,232.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.







AD7328 pdf, 数据表
AD7328
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CS 1
DIN 2
DGND 3
AGND 4
REFIN/OUT 5
VSS 6
VIN0 7
VIN1 8
VIN4 9
VIN5 10
AD7328
TOP VIEW
(Not to Scale)
20 SCLK
19 DGND
18 DOUT
17 VDRIVE
16 VCC
15 VDD
14 VIN2
13 VIN3
12 VIN6
11 VIN7
Figure 3. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7328 and frames the serial data transfer.
2 DIN Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the
register on the falling edge of SCLK (see the Registers section).
3, 19
DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7328. The DGND and AGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
4
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7328. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
5 REFIN/OUT Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the
AD7328. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor
should be placed on the reference pin. Alternatively, the internal reference can be disabled and an
external reference applied to this input. On power-up, the external reference mode is the default
condition (see the Reference section).
6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
7, 8, 14, 13, 9, 10,
12, 11
VIN0 to VIN7
Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the Channel Address Bit ADD2
through Bit ADD0 in the control register. The inputs can be configured as eight single-ended inputs,
four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs.
The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and
Bit Mode 0, in the control register. The input range on each input channel is controlled by program-
ming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each
analog input channel when a +2.5 V reference voltage is used (see the Reference section).
15 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
16 VCC Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7328.
This supply should be decoupled to AGND. Specifications apply from VCC = 4.75 V to 5.25 V.
17
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VCC,
but it should not exceed VCC by more than 0.3 V.
18
DOUT
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The
data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data.
The data is provided MSB first (see the Serial Interface section).
20
SCLK
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the
AD7328. This clock is also used as the clock source for the conversion process.
Rev. A | Page 8 of 36







AD7328 equivalent, schematic
AD7328
VIN0
B CS
A SW1
CAPACITIVE
DAC
COMPARATOR
SW2
CONTROL
LOGIC
AGND
Figure 24. ADC Conversion Phase (Single-Ended)
Figure 25 shows the differential configuration during the ac-
quisition phase. For the conversion phase, SW3 opens and SW1
and SW2 move to Position B (see Figure 26). The output
impedances of the source driving the VIN+ and VIN− pins must
match; otherwise, the two inputs have different settling times,
resulting in errors.
VIN+
VIN
B CS
A SW1
A SW2
B CS
CAPACITIVE
DAC
COMPARATOR
SW3
CONTROL
LOGIC
VREF
CAPACITIVE
DAC
Figure 25. ADC Differential Configuration During Acquisition Phase
VIN+
VIN
B CS
A SW1
A SW2
B CS
CAPACITIVE
DAC
COMPARATOR
SW3
CONTROL
LOGIC
VREF
CAPACITIVE
DAC
Figure 26. ADC Differential Configuration During Conversion Phase
Output Coding
The AD7328 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When operating
in sequence mode, the output coding for each channel in the
sequence is the value written to the coding bit during the last
write to the control register.
Transfer Functions
The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size
is dependent on the analog input range selected.
Table 7. LSB Sizes for Each Analog Input Range
Input Range Full-Scale Range/8192 Codes LSB Size
±10 V
20 V
2.441 mV
±5 V 10 V
1.22 mV
±2.5 V
5V
0.61 mV
0 V to +10 V
10 V
1.22 mV
The ideal transfer characteristic for the AD7328 when twos
complement coding is selected is shown in Figure 27. The ideal
transfer characteristic for the AD7328 when straight binary coding
is selected is shown in Figure 28.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
–FSR/2 + 1LSB
AGND + 1LSB
AGND – 1LSB +FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB UNIPOLAR RANGE
ANALOG INPUT
Figure 27. Twos Complement Transfer Characteristic (Bipolar Ranges)
111...111
111...110
111...000
011...111
000...010
000...001
000...000
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB
+FSR – 1LSB
ANALOG INPUT
BIPOLAR RANGES
UNIPOLAR RANGE
Figure 28. Straight Binary Transfer Characteristic (Bipolar Ranges)
ANALOG INPUT STRUCTURE
The analog inputs of the AD7328 can be configured as single-
ended, true differential, or pseudo differential via the control
register mode bits (see Table 10). The AD7328 can accept true
bipolar input signals. On power-up, the analog inputs operate as
eight single-ended analog input channels. If true differential or
pseudo differential is required, a write to the control register is
necessary after power-up to change this configuration.
Figure 29 shows the equivalent analog input circuit of the
AD7328 in single-ended mode. Figure 30 shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
VDD
VIN0
D
C1 D
R1 C2
VSS
Figure 29. Equivalent Analog Input Circuit (Single-Ended)
Rev. A | Page 16 of 36










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