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PDF ( 数据手册 , 数据表 ) AD2S1205

零件编号 AD2S1205
描述 12-Bit RDC
制造商 Analog Devices
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AD2S1205 数据手册, 描述, 功能
FEATURES
Complete monolithic resolver-to-digital converter (RDC)
Parallel and serial 12-bit data ports
System fault detection
±11 arc minutes of accuracy
Input signal range: 3.15 V p-p ± 27%
Absolute position and velocity outputs
1250 rps maximum tracking rate, 12-bit resolution
Incremental encoder emulation (1024 pulses/rev)
Programmable sinusoidal oscillator on board
Single-supply operation (5.00 V ± 5%)
−40°C to +125°C temperature rating
44-lead LQFP
4 kV ESD protection
Qualified for automotive applications
APPLICATIONS
Automotive motion sensing and control
Hybrid-electric vehicles
Electric power steering
Integrated starter generator/alternator
Industrial motor control
Process control
GENERAL DESCRIPTION
The AD2S1205 is a complete 12-bit resolution tracking
resolver-to-digital converter that contains an on-board
programmable sinusoidal oscillator providing sine wave
excitation for resolvers.
The converter accepts 3.15 V p-p ± 27% input signals on the Sin
and Cos inputs. A Type II tracking loop is employed to track the
inputs and convert the input Sin and Cos information into a digital
representation of the input angle and velocity. The maximum
tracking rate is a function of the external clock frequency. The
performance of the AD2S105 is specified across a frequency
range of 8.192 MHz ± 25%, allowing a maximum tracking rate
of 1250 rps.
12-Bit RDC
with Reference Oscillator
AD2S1205
EXCITATION
OUTPUTS
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
PINS
CRYSTAL
AD2S1205
REFERENCE
OSCILLATOR
(DAC)
VOLTAGE
REFERENCE
INTERNAL
CLOCK
GENERATOR
SYNTHETIC
REFERENCE
INPUTS
FROM
RESOLVER
ADC
ADC
TYPE II TRACKING LOOP
FAULT
DETECTION
ENCODER
EMULATION
OUTPUTS
POSITION REGISTER VELOCITY REGISTER
ENCODER
EMULATION
MULTIPLEXER
DATA BUS OUTPUT
FAULT
DETECTION
OUTPUTS
RESET
DATA I/O
Figure 1.
PRODUCT HIGHLIGHTS
1. Ratiometric Tracking Conversion. The Type II tracking
loop provides continuous output position data without
conversion delay. It also provides noise immunity and
tolerance of harmonic distortion on the reference and
input signals.
2. System Fault Detection. A fault detection circuit can sense
loss of resolver signals, out-of-range input signals, input
signal mismatch, or loss of position tracking.
3. Input Signal Range. The Sin and Cos inputs can accept
differential input voltages of 3.15 V p-p ± 27%.
4. Programmable Excitation Frequency. Excitation frequency
is easily programmable to 10 kHz, 12 kHz, 15 kHz, or 20 kHz
by using the frequency select pins (the FS1 and FS2 pins).
5. Triple Format Position Data. Absolute 12-bit angular position
data is accessed via either a 12-bit parallel port or a 3-wire
serial interface. Incremental encoder emulation is in standard
A-quad-B format with direction output available.
6. Digital Velocity Output. 12-bit signed digital velocity accessed
via either a 12-bit parallel port or a 3-wire serial interface.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.







AD2S1205 pdf, 数据表
AD2S1205
RESOLVER FORMAT SIGNALS
Vr = Vp × Sin(ωt)
R1
S2
Va = Vs × Sin(ωt) × Cos(θ)
θ
R2
S4
S1 S3
Vb = Vs × Sin(ωt) × Sin(θ)
R1
R2
Vr = Vp × Sin(ωt)
θ
S2
Va = Vs × Sin(ωt) × Cos(θ)
S4
S1 S3
Vb = Vs × Sin(ωt) × Sin(θ)
(A) CLASSICAL RESOLVER
(B) VARIABLE RELUCTANCE RESOLVER
Figure 3. Classical Resolver vs. Variable Reluctance Resolver
A classical resolver is a rotating transformer that typically has a
primary winding on the rotor and two secondary windings on
the stator. A variable reluctance resolver, on the other hand, has the
primary and secondary windings on the stator and no windings
on the rotor, as shown in Figure 3; however, the saliency in this
rotor design provides the sinusoidal variation in the secondary
coupling with the angular position. For both designs, the resolver
output voltages (S3 − S1, S2 − S4) are as follows:
S3 S1 = E0Sin(ωt)× Sinθ
(1)
S2 S4 = E0Sin(ωt)× Cosθ
where:
θ is the shaft angle.
Sin(ωt) is the rotor excitation frequency.
E0 is the rotor excitation amplitude.
The stator windings are displaced mechanically by 90° (see
Figure 3). The primary winding is excited with an ac reference.
The amplitude of subsequent coupling onto the secondary
windings is a function of the position of the rotor (shaft)
relative to the stator. The resolver therefore produces two
output voltages (S3 − S1, S2 − S4), modulated by the sine and
cosine of the shaft angle. Resolver format signals refer to the
signals derived from the output of a resolver, as shown in
Equation 1. Figure 4 illustrates the output format.
S2 – S4
(COSINE)
S3 – S1
(SINE)
R2 – R4
(REFERENCE)
90°
180°
270°
θ
Figure 4. Electrical Resolver Representation
360°
Rev. A | Page 8 of 20







AD2S1205 equivalent, schematic
AD2S1205
INCREMENTAL ENCODER OUTPUTS
The A, B, and NM incremental encoder emulation outputs are
free running and are valid if the resolver format input signals
applied to the converter are valid.
The AD2S1205 emulates a 1024-line encoder, meaning that, in
terms of the converter resolution, one revolution produces 1024 A
and B pulses. Pulse A leads Pulse B for increasing angular rotation
(clockwise direction). The addition of the DIR output negates
the need for external A and B direction decode logic. The DIR
output indicates the direction of the input rotation and is high
for increasing angular rotation. DIR can be considered an asyn-
chronous output that can make multiple changes in state between
two consecutive LSB update cycles. This occurs when the direction
of the rotation of the input changes but the magnitude of the
rotation is less than 1 LSB.
The north marker pulse is generated as the absolute angular
position passes through zero. The north marker pulse width is
set internally for 90° and is defined relative to the A cycle.
Figure 9 details the relationship between A, B, and NM.
A
B
NM
Figure 9. A, B, and NM Timing for Clockwise Rotation
Unlike incremental encoders, the AD2S1205 encoder output is
not subject to error specifications such as cycle error, eccentricity,
pulse and state width errors, count density, and phase ϕ. The
maximum speed rating (n) of an encoder is calculated from its
maximum switching frequency (fMAX) and its pulses per revo-
lution (PPR).
n = 60 × fMAX
PPR
(9)
The A and B pulses of the AD2S1205 are initiated from the inter-
nal clock frequency, which is exactly half the external CLKIN
frequency. With a nominal CLKIN frequency of 8.192 MHz,
the internal clock frequency is 4.096 MHz. The equivalent
encoder switching frequency is
1/ 4 × 4.096 MHz = 1.024 MHz (4 Updates = 1 Pulse) (10)
For 12 bits, the PPR is 1024. Therefore, the maximum speed (n)
of the AD2S1205 with a CLKIN of 8.192 MHz is
60 ×1,024,000
n = = 60,000 rpm
1024
(11)
To achieve the maximum speed of 75,000 rpm, select an
external CLKIN of 10.24 MHz to produce an internal clock
frequency equal to 5.12 MHz.
This compares favorably with encoder specifications, which
state fMAX as 20 kHz (photo diodes) to 125 kHz (laser based),
depending on the type of light system used. A 1024-line laser-
based encoder has a maximum speed of 7300 rpm.
The inclusion of A and B outputs allows an AD2S1205 and
resolver-based solution to replace optical encoders directly
without the need to change or upgrade the user’s existing
application software.
SUPPLY SEQUENCING AND RESET
The AD2S1205 requires an external reset signal to hold the
RESET input low until VDD is within the specified operating
range of 4.5 V to 5.5 V.
The RESET pin must be held low for a minimum of 10 μs after
VDD is within the specified range (shown as tRST in Figure 10).
Applying a RESET signal to the AD2S1205 initializes the output
position to a value of 0x000 (degrees output through the parallel,
serial, and encoder interfaces) and causes LOS to be indicated
(LOT and DOS pins pulled low), as shown in Figure 10.
Failure to apply the correct power-up/reset sequence may result
in an incorrect position indication.
After a rising edge on the RESET input, the device must be
allowed at least 20 ms (shown as tTRACK in Figure 10) for the
internal circuitry to stabilize and the tracking loop to settle to
the step change of the input position. After tTRACK, a SAMPLE
pulse must be applied, which in turn releases the LOT and DOT
pins to the state determined by the fault detection circuitry and
provides valid position data at the parallel and serial outputs.
(Note that if position data is acquired via the encoder outputs,
it can be monitored during tTRACK.)
The RESET pin is then internally pulled up.
VDD 4.75V
RESET
tRST
tTRACK
SAMPLE
LOT
DOS
VALID
OUTPUT
DATA
Figure 10. Power Supply Sequencing and Reset
Rev. A | Page 16 of 20










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