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PDF ( 数据手册 , 数据表 ) ZL50023

零件编号 ZL50023
描述 Enhanced 4 K Digital Switch
制造商 Zarlink Semiconductor
LOGO Zarlink Semiconductor LOGO 


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ZL50023 数据手册, 描述, 功能
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ZL50023
Enhanced 4 K Digital Switch
Data Sheet
Features
• 4096 channel x 4096 channel non-blocking digital
Time Division Multiplex (TDM) switch at
8.192 Mbps and 16.384 Mbps or using a
combination of ports running at 2.048 Mbps,
4.096 Mbps, 8.192 Mbps and 16.384 Mbps
• 32 serial TDM input, 32 serial TDM output
streams
• Output streams can be configured as bi-
directional for connection to backplanes
• Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
• Per-stream input and output data rate conversion
selection at 2.048 Mbps, 4.096 Mbps 8.192 Mbps
or 16.384 Mbps. Input and output data rates can
differ
• Per-stream high impedance control outputs
(STOHZ) for 16 output streams
• Per-stream input bit delay with flexible sampling
point selection
October 2004
Ordering Information
ZL50023GAC 256-ball PBGA
ZL50023QCC 256-lead LQFP
-40°C to +85°C
• Per-stream output bit and fractional bit
advancement
• Per-channel ITU-T G.711 PCM A-Law/µ-Law
Translation
• Four frame pulse and four reference clock outputs
• Three programmable delayed frame pulse outputs
• Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
• Input frame pulses: 61 ns, 122 ns, 244 ns
• Per-channel constant or variable throughput delay
for frame integrity and low latency applications
STi[31:0]
FPi
CKi
MODE_4M0
MODE_4M1
VDD_CORE
VDD_IO
VDD_COREA VDD_IOA
VSS
RESET
ODE
S/P Converter
Data Memory
P/S Converter
Input Timing
Connection Memory
Output HiZ
Control
Output Timing
STio[31:0]
STOHZ[15:0]
FPo[3:0]
CKo[3:0]
FPo_OFF[2:0]
Internal Registers &
Microprocessor Interface
Test Port
Figure 1 - ZL50023 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.







ZL50023 pdf, 数据表
2.2 QFP Pinout
ZL50023
Data Sheet
STi28
STi29
VDD_IO
STi30
STi31
STi_8
VSS
STi_9
STi_10
STi_11
STi_12
STi_13
STi_14
STi_15
VDD_IO
IC_GND
VSS
IC_Open
RESET
TDo
VDD_CORE
VSS
NC
VSS
VDD_COREA
VSS
NC
VDD_IOA
NC
VSS
VSS
VDD_COREA
NC
VDD_IOA
CKo3
VSS
NC
VSS
VDD_COREA
VSS
VDD_CORE
TMS
VSS
NC
NC
TCK
TRST
TDi
VDD_IO
VSS
STi_16
STi_17
STi_18
STi_19
STi_20
STi_21
VDD_IO
STi_22
VSS
STi_23
STio_24
STio_25
STio_26
STio_27
192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130
128
194
126
196
124
198
122
200
120
202
118
204
116
206
114
208
112
210
110
212
108
214
106
216
104
218
102
220
100
222
98
224
96
226
94
228
92
230
90
232
88
234
86
236
84
238
82
240
80
242
78
244
76
246
74
248
72
250
70
252
68
254
66
256
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
STio_19
STio_18
STio_17
STio_16
STOHZ_15
VSS
STOHZ_14
VDD_IO
STOHZ_13
STOHZ_12
STio_15
STio_14
STio_13
STio_12
VSS
VDD_IO
FPo3
VSS
FPo2
VDD_CORE
FPo_OFF2
IC_GND
FPo1
IC_Open
FPo_OFF1
VSS
FPo0
VDD_IO
FPo_OFF0
A13
A12
VSS
A11
VDD_CORE
A10
A9
A8
A7
A6
A5
A4
A3
A2
VSS
A1
VDD_CORE
A0
VSS
IC_Open
VDD_IO
STOHZ_11
STOHZ_10
STOHZ_9
STOHZ_8
STio_11
STio_10
STio_9
VSS
STio_8
VDD_IO
NC
NC
NC
NC
Figure 3 - ZL50023 256-Lead 28 mm x 28 mm LQFP (top view)
8
Zarlink Semiconductor Inc.







ZL50023 equivalent, schematic
ZL50023
Data Sheet
32 input streams were operating at 16.384 Mbps (256 channels per stream), this would result in 8192 channels.
Memory limitations prevent the device from operating at this capacity. A maximum capacity of 4096 channels will
occur if half of the total streams are operating at 16.384 Mbps or all streams are operating at 8.192 Mbps. With all
streams operating at 4.09 Mbps, the switching capacity is reduced to 2048 channels. And with all streams operating
at 2.048 Mbps, the capacity will be further reduced to 1024 channels. However, as each stream can be
programmed to a different data rate, any combination of data rates can be achieved, as long as the total channel
count does not exceed 4096 channels. It should be noted that only full stream can be programmed for use. The
device does not allow fractional streams.
5.1 External High Impedance Control, STOHZ0 - 15
There are 16 external high impedance control signals, STOHZ0 - 15, that are used to control the external drivers for
per-channel high impedance operations. Only the first sixteen ST-BUS/GCI-Bus (STio0 - 15) outputs are provided
with corresponding STOHZ signals. The STOHZ outputs deliver the appropriate number of control timeslot
channels based on the output stream data rate. Each control timeslot lasts for one channel time. When the ODE pin
is high and the OSB (bit 2) of the Control Register (CR) is also high, STOHZ0 - 15 are enabled. When the ODE pin,
OSB (bit 2) of the Control Register (CR) or the RESET pin is low, STOHZ0 - 15 are driven high, together with all the
ST-BUS/GCI-Bus outputs being tristated. Under normal operation, the corresponding STOHZ outputs of any
unused ST-BUS/GCI-Bus channel (high impedance) are driven high. Refer to Figure 16 on page 26 for a
diagrammatical explanation.
5.2 Input Clock (CKi) and Input Frame Pulse (FPi) Timing
The frequency of the input clock (CKi) for the ZL50023 depends on the timing mode selected. In divided clock mode
CKi, must be at least twice the highest input or output data rate. For example, if the highest input data rate is
4.096 Mbps and the highest output data rate is 8.192 Mbps, the input clock, CKi, must be 16.384 MHz, which is
twice the highest overall data rate. The only exception to this is for 16.384 Mbps input or output data. In this case,
the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi. In multiplied clock
mode the frequency of CKi must be at least twice the highest input data rate regardless of the output data rate. An
APLL is used to multiple CKi to generate an internal clock that is used to clock the output clocks and STio streams.
Following the example above, if the highest input data rate is 4.096 Mbps, the input clock, CKi, must be 8.192 MHz,
regardless of the output data rate. The only exception to this is for 16.384 Mbps input or output data. In this case,
the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi.
In either mode the user has to program the CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) to indicate the width
of the input frame pulse and the frequency of the input clock supplied to the device.
Highest Input or Output
Data Rate
16.384 Mbps or 8.192 Mbps
4.096 Mbps
2.048 Mbps
CKIN 1-0 Bits
Input Clock Rate (CKi) Input Frame Pulse (FPi)
00 16.384 MHz
01 8.192 MHz
10 4.096 MHz
Table 1 - CKi and FPi Configurations
8 kHz (61 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (244 ns wide pulse)
16
Zarlink Semiconductor Inc.










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