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PDF ( 数据手册 , 数据表 ) NX29F010

零件编号 NX29F010
描述 ULTRA-FAST SECTORED FLASH MEMORY
制造商 NexFlash
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NX29F010 数据手册, 描述, 功能
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NX29F010
1M-BIT (128K x 8-bit)
CMOS, 5.0V Only
ULTRA-FAST SECTORED FLASH MEMORY
JUNE 2000
FEATURES
• Ultra-fast Performance
– 35, 45, 55, 70, and 90 ns max. access times
• Temperature Ranges
– Commercial 0oc-70oc
– Industrial -40oc-85oc
• Single 5V-only Power Supply
– 5V ± 10% for Read, Program, and Erase
• CMOS Low Power Consumption
– 20 mA (typical) active read current
– 30 mA (typical) Program/Erase current
• Compatible with JEDEC-Standard Pinouts
– 32-pin DIP, PLCC, TSOP
• Program/function Compatible with AM29F010
– No system firmware changes
– Uses same PROM programer algorithm
• Flexible sector architecture
– Erase any of eight uniform sectors or full chip erase
– Sector protection/unprotection using PROM
programming equipment
• 100,000 Program/Erase cycles
• Embedded algorithms
– Automatically programs and verifies data at
specified address
– Auto-programs and erases the chip or any
designated sector
• Data/Polling and Toggle Bits
– Detect program or erase cycle completion
DESCRIPTION
The NexFlash NX29F010 is a 1 Megabit (131,072 bytes)
single 5.0V-only Sectored Flash Memory. The NX29F010
provides in-system programming with the standard system
5.0V-only Vcc supply and can be programmed or erased in
standard PROM programmers.
The NX29F010 offers access times of 35, 45, 55, 70, and
90 ns allowing high-speed controller and DSPs' to operate
without wait states. Byte-wide data appears on DQ0-DQ7.
Separate chip enable (CE), write enable (WE), and output
enable (OE) controls eliminates bus contention.
Power consumption is greatly reduced when the system
places the device into the Standby Mode.
The device is offered in 32-pin PLCC, TSOP, and PDIP
packages.
Principles of Operation
Only a single 5.0V power supply is required for both read and
write functions. Program or erase operations do not require
12.0V VPP. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC single power supply Flash standard. Commands
are written to the command register using standard micro-
processor write timings. Register contents serve as input to
an internal state machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and
erase operations. Reading data out of the device is similar
to reading from other Flash or EPROM devices.
Executing the Program Command Sequence invokes the
Embedded Program Algorithm, an internal algorithm that
automatically times the program pulse widths and verifies
proper cell margin.
This document contains PRELIMINARY data. NexFlash reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We
assume no responsibility for any errors which may appear in this publication. © Copyright 1998, NexFlash Technologies, Inc..
NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©
1







NX29F010 pdf, 数据表
NX29F010
Commands written to the device while the Embedded
Program Algorithm is in progress are ignored.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a '0' back
to a '1'. Attempting to do so may halt the operation and set
the error status bit, DQ5, to '1', or cause the Data Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is still
'0'. Only erase operations can convert a '0' to a '1'.
Note: See Command Definitions (Table 5) for program
command sequence.
START
WRITE PROGRAM
COMMAND
SEQUENCE
EMBEDDED
PROGRAM
ALGORITHM
IN PROGRESS
DATA POLL
FROM
SYSTEM
VERIFY
DATA?
YES
NO
INCREMENT
ADDRESS
NO LAST
ADDRESS?
YES
PROGRAMMING
COMPLETE
Figure 5. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a setup command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory
for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings
during these operations. The Command Definitions table
shows the address and data requirements for the chip erase
command sequence.
Commands written to the chip while the Embedded Erase
Algorithm is in progress are ignored.
The system can determine the status of the erase operation
by using DQ7 or DQ6. See "Write Operation Status" for
information on these status bits. When the Embedded
Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
Figure 6 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in "AC Charac-
teristics" for parameters, and to the Chip/Sector Erase
Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a setup command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions Table (Table 5) shows the address and data
requirements for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The embedded erase algorithm
automatically programs and verifies the sector for an all
zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
8 NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©







NX29F010 equivalent, schematic
NX29F010
TEST CONDITIONS
Table 6. AC Test Specifications
Test Conditions
35 ns AllOthers Unit
Output Load
1 TTL Gate
Output Load Capacitance, CL 30
(including jig capacitance)
100 pF
Input Rise and Fall Times
5
20 ns
Input Pulse Levels
0 to 3.0 0.45 to 2.4 V
Input Timing Measurement
ReferenceLevels
1.5
0.8 V
OutputTimingMeasurement 1.5
ReferenceLevels
2.0 V
DEVICE
UNDER
TEST
CL
Vcc = 5.0V
2.7K
6.2K
Figure 12. Test Setup
AC CHARACTERISTICS: ERASE AND PROGRAM
Std.
Symbol Parameter
tWC Write Cycle Time(1)
-35
Min. Max.
35
tAS Address Setup Time
0
tAH Address Hold Time
30
tDS Data Setup Time
15
tDH Data Hold Time
0
tGHWL Read Recovery Time before Write 0
(OE HIGH to WE LOW)
tCS CE Setup Time
tCH CE Hold Time
0
0
tWP Write Pulse Width
20
tWPH Write Pulse Width HIGH
20
tWHWH1 Byte Programming Operation(2) 20
tWHWH2 Sector Erase Operation(2)
1.0
tVCS VCC Setup Time(1)
50
-45
Min. Max.
45
0
35
20
0
0
0
0
25
20
20
1.0
50
Note:
1. Not 100% tested.
-55
Min. Max.
45
0
45
20
0
0
0
0
30
20
20
1.0
1.0
-70
Min. Max.
45
0
45
30
0
0
0
0
35
20
20
1.0
1.0
-90
Min. Max. Unit
90 ns
0 ns
45 ns
45 ns
0 ns
0 ns
0
0
45
20
20
1.0
1.0
ns
ns
ns
ns
µs
sec
µs
16 NexFlash Technologies, Inc.
NXPF001F-0600
06/22/00 ©










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