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零件编号 | P75N02LD | ||
描述 | N-Channel Logic Level Enhancement Mode Field Effect Transistor | ||
制造商 | Niko | ||
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NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P75N02LD
TO-252 (D2PAK)
PRODUCT SUMMARY
V(BR)DSS
RDS(ON)
25 5mΩ
ID
75A
D
G
1. GATE
2. DRAIN
3. SOURCE
S
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current1
TC = 25 °C
TC = 100 °C
Avalanche Current
Avalanche Energy
L = 0.1mH
Repetitive Avalanche Energy2
L = 0.05mH
Power Dissipation
TC = 25 °C
TC = 100 °C
Operating Junction & Storage Temperature Range
Lead Temperature (1/16” from case for 10 sec.)
VGS
ID
IDM
IAR
EAS
EAR
PD
Tj, Tstg
TL
LIMITS
±20
75
50
170
60
140
5.6
65
38
-55 to 150
275
UNITS
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
Junction-to-Case
RθJC
Junction-to-Ambient
RθJA
Case-to-Heatsink
RθCS
1Pulse width limited by maximum junction temperature.
2Duty cycle ≤ 1%
TYPICAL
0.6
MAXIMUM
2.3
62.5
UNITS
°C / W
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
V(BR)DSS
VGS(th)
IGSS
IDSS
STATIC
VGS = 0V, ID = 250µA
VDS = VGS, ID = 250µA
VDS = 0V, VGS = ±20V
VDS = 20V, VGS = 0V
VDS = 20V, VGS = 0V, TJ = 125 °C
LIMITS
MIN TYP MAX
UNIT
25
1 1.5
3
V
±250 nA
25
250 µA
1 AUG-02-2001
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页数 | 3 页 | ||
下载 | [ P75N02LD.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
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