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PDF ( 数据手册 , 数据表 ) W536060A

零件编号 W536060A
描述 (W536xx0A) VOICE/ MELODY / LCD CONTROLLER
制造商 Winbond
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W536060A 数据手册, 描述, 功能
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GENERAL DESCRIPTION
The W536XXXA, a member of ViewTalkTM family, is a high-performance 4-bit micro-controller (uC) with
built-in speech unit, melody unit and 64seg * 16 com LCD driver unit which includes internal regulator
,pump circuit and dedicated two pages LCD RAM. The 4-bit uC core contains dual clock source, 4-bit
ALU, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and
8-level nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with
maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM) , is capable of expanding to
512 seconds speech addressed by external memory W55XXX with serial bus interface. It can be
implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone
output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation.
It is ideal for games, educational toys, remote controllers, watches, clocks and other application
products which incorporate both LCD display and speech.
Body
W536030A W536060A W536090A
W536120A
Voice
30 sec
60 sec
90 sec
120 sec
I/O pad
4I/O,8I
8I/O, 8I
8I/O, 8I , 8O
8I/O, 8I, 8O
(RA/RC/RD)
(RA/RB/RC/RD) (RA/RB/RC/RD/RE/RF) (RA/RB/RC/RD/RE/RF
)
WDT
disable/Enable
Y
Y
Y
Y
(Mask Option)
Sub-clock
RC/XTAL mode
Y
Y
Y
Y
(Mask Option)
RD port shared as
serial bus
Y(1) Y(1)
N
N (2)
(Mask Option)
Tri-state serial bus
(Mask Option) ( 3)
Y
Y
N
N
Cascaded Voice
ROM through Y(1) Y(1)
N
Y
serial bus (2)
(1) Share 3 pads of RD port (RD1/RDP, RD2/SPDATA and RD3/WRP)
(2) Dedicate serial bus 3 pads (RDP, SPDATA and WRP) to interface with W55XXX. Cascaded
Voice ROM can help to expand voice up to 512 sec by W55XXX chip.
(3) Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this
mask option is disabled to get minimum power consumption in general.
FEATURES
Operating voltage: 2.4 volt ~ 5.5 volt
Watch dog disabled/enabled by mask option
Dual clock operating system
Main clock with RC/Crystal (400 KHz to 4 MHz)
Sub-clock with 32.768 KHz RC/Crystal by mask option
Publication Release Date: April 2000
- 1 - Revision A6







W536060A pdf, 数据表


  
DAC output Current
IDAC VDD=3v, RL=100ohm
-4
-5 -6 mA
LCD Supply Current
ILCD No Load, All Seg. ON
-
50 -
µA
COM/SEG On Resistor
RON IOH = ± 50 µA
5K 10K
V2 Pad Output Voltage
V2 Pad Output Deviation (9)
V2 Pad Voltage Step
V6 Pad Output Voltage
(LCD's VLCD depended on
VRR
VD1
VR2
VLCD
Depended on LCDM4
No Load
LCDM4 increased 1
1/4 Bias & no load
0.7 1.45 V
±5 %
50 mV
3.8 3.85 3.9 V
* V2 * V2 * V2
LCDM4 register) (9)
1/5 Bias & no load
4.75 4.8 4.85
* V2 * V2 * V2
V2 input voltage
VEXT LCDM3.3=1
1.5 V
(8) PWM current deviation will be ±20%.
(9) Deviation is governed by LCD dot size. More larger LCD dot will get larger deviation..
AC CHARATERISTICS
(VDDVSS = 3.0V, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C, STN LCD
on with dot size 0.5mm*0.5mm; unless otherwise specified)
PARAMETER
SYM. CONDITIONS
MIN. TYP.
MAX. UNIT
Sub-clock Frequency
FSUB
Crystal type and X32IN
and X32O with 17pF
external cap.
32768
Hz
Main-clock Frequency
FM
RC type/Crystal type
400K -
4M Hz
Chip Operation Frequency FOSC SCR0.0=1,FSYS=FSUB
32768
Hz
SCR0.0=0;FSYS= FMAIN 400K -
4M
Instruction Cycle Time
TCYC One machine cycle
- 4/FOSC - S
Reset Active Width
Interrupt Active Width
Main clock RC frequency
(10)
Sub-Clock Ring Oscillator
Sub-Clock Oscillation
Stable Time @ Cold Start
TRAW
TIAW
FRXIN
FRSUB
FSTOP
FOSC = 32.768 KHz
FOSC = 32.768 KHz
RXIN =680K
RXIN =330K
RXIN =200K
RXIN =130K
RSUB=680K
RSUB=680K
1-
1-
1M
2M
3M
4M
32
0.8
- µS
- µS
Hz
KHz
1S
Frequency Deviation of
f
main-clock FRXIN 2MHz f
f(3V) f(2.4V)
f(3V)
10 %
Frequency Deviation of
f
main-clock FRXIN = 3 MHz f
f(3V) f(2.4V)
f(3V)
15 %
Frequency Deviation of
f
main-clock FRXIN =4 MHz f
f(3V) f(2.4V)
f(3V)
20 %
ROSC Frequency
Frequency Deviation of
FROSC = 3MHz
FROSC
f
f
ROSC=680K
f(3V) f(2.4V)
f(3V)
3 MHz
7.5 %
Frame frequency
FLCD LCDM1=0111 b(default)
64
Hz
(10) The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor
Publication Release Date:April 2000
- 8 - Revision A6














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