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PDF ( 数据手册 , 数据表 ) NS16C2752

零件编号 NS16C2752
描述 (NS16C2552 / NS16C2752) Dual UART
制造商 National Semiconductor
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NS16C2752 数据手册, 描述, 功能
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PRELIMINARY
August 2006
NS16C2552/NS16C2752
Dual UART with 16-byte/64-byte FIFO’s and up to
5 Mbit/s Data Rate
1.0 General Description
The NS16C2552 and NS16C2752 are dual channel Univer-
sal Asynchronous Receiver/Transmitter (DUART). The foot-
print and the functions are compatible to the PC16552D,
while new features are added to the UART device. These
features include low voltage support, 5V tolerant inputs,
enhanced features, enhanced register set, and higher data
rate.
The two serial channels are completely independent of each
other, except for a common CPU interface and crystal input.
On power-up both channels are functionally identical to the
PC16552D. Each channel can operate with on-chip transmit-
ter and receiver FIFO’s (in FIFO mode).
In the FIFO mode each channel is capable of buffering 16
bytes (for NS16C2552) or 64 bytes (for NS16C2752) of data
in both the transmitter and receiver. The receiver FIFO also
has additional 3 bits of error data per location. All FIFO
control logic is on-chip to minimize system software over-
head and maximize system efficiency.
To improve the CPU processing bandwidth, the data trans-
fers between the DUART and the CPU can be done using
DMA controller. Signaling for DMA transfers is done through
two pins per channel (TXRDY and RXRDY). The RXRDY
function is multiplexed on one pin with the OUT2 and BAUD-
OUT functions. The configuration is through Alternate Func-
tion Register.
The fundamental function of the UART is converting be-
tween parallel and serial data. Serial-to-parallel conversion
is done on the UART receiver and parallel-to-serial conver-
sion is done on the transmitter. The CPU can read the
complete status of each channel at any time. Status infor-
mation reported includes the type and condition of the trans-
fer operations being performed by the DUART, as well as
any error conditions (parity, overrun, framing, or break inter-
rupt).
The NS16C2552 and NS16C2752 include one program-
mable baud rate generator for each channel. Each baud rate
generator is capable of dividing the clock input by divisors of
1 to (216 - 1), and producing a 16X clock for driving the
internal transmitter logic and for receiver sampling circuitry.
The NS16C2552 and NS16C2752 have complete MODEM-
control capability, and a processor-interrupt system. The
interrupts can be programmed by the user to minimize the
processing required to handle the communications link.
2.0 Features
n Dual independent UART
n Up to 5 Mbits/s data transfer rate
n 2.97 V to 5.50 V operational Vcc
n 5 V tolerant I/Os in the entire supply voltage range
n Industrial Temperature: -40˚C to 85˚C
n Default registers are identical to the PC16552D
n NS16C2552/NS16C2752 is pin-to-pin compatible to
NSC PC16552D, EXAR ST16C2552, XR16C2552, XR
16L2552, and Phillips SC16C2552B
n NS16C2752 is compatible to EXAR XR16L2752, and
register compatible to Phillips SC16C752
n Auto Hardware Flow Control (Auto-CTS, Auto-RTS)
n Auto Software Flow Control (Xon, Xoff, and Xon-any)
n Fully programmable character length (5, 6, 7, or 8) with
even, odd, or no parity, stop bit
n Adds or deletes standard asynchronous communication
bits (start, stop, and parity) to or from the serial data
n Independently controlled and prioritized transmit and
receive interrupts
n Complete line status reporting capabilities
n Line break generation and detection
n Internal diagnostic capabilities
— Loopback controls for communications link fault
isolation
— Break, parity, overrun, framing error detection
n Programmable baud generators divide any input clock
by 1 to (216 - 1) and generate the 16 X clock
n IrDA v1.0 wireless Infrared encoder/decoder
n DMA operation (TXRDY/RXRDY)
n Concurrent write to DUART internal register channels 1
and 2
n Multi-function output allows more package functions with
fewer I/O pins
n 44-PLCC or 48-TQFP package
© 2006 National Semiconductor Corporation DS202048
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NS16C2752 pdf, 数据表
5.0 Pin Descriptions (Continued)
5.3 CLOCK AND RESET
Signal
Name
XIN
XOUT
MR
Type
I
O
I
PLCC
Pin #
11
13
21
TQFP
Pin #
5
7
16
Description
External Crystal Input:
XIN input is used in conjunction with XOUT to form a feedback circuit for
the baud rate generator’s oscillator. If a clock signal is generated
off-chip, then it should drive the baud rate generator through this pin.
Refer to Section 7.1 CLOCK INPUT.
External Crystal Output:
XOUT output is used in conjunction with XIN to form a feedback circuit
for the baud rate generator’s oscillator. If the clock signal is generated
off-chip, then this pin is unused. Refer to Section 7.1 CLOCK INPUT.
Master Reset:
When MR input is high, it clears all the registers including Tx and Rx
serial shift registers (except the Receiver Buffer, Transmitter Holding,
and Divisor Latches). The output signals, such as OUT2, RTS, DTR,
INTR, and SOUT are also affected by an active MR input. (Refer to
Table 26 and Section 7.2 RESET).
5.4 POWER AND GROUND
Signal
Name
VCC
GND
NC
Type
I
I
I
PLCC
Pin #
33
44
12
22
N/A
TQFP
Pin #
29
42
6
17
19
37
Description
VCC:
+2.97V to +5.5V supply.
GND:
Device ground reference.
No Connection:
These pins are only available on the TQFP package.
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NS16C2752 equivalent, schematic
6.0 Register Set (Continued)
6.6 LINE CONTROL REGISTER (LCR)
The system programmer specifies the format of the asyn-
chronous data communications exchange and sets the Divi-
sor Latch Access bit via the Line Control Register (LCR).
This is a read and write register.
TABLE 10. LCR (0x3)
Bit Name
R/W
Bit
Default
Def
Description
7
Divisor Latch
R/W
Divisor Latch Access Bit (DLAB)
Ena 0 This bit must be set (logic 1) to access the Divisor Latches of the Baud Generator
and the Alternate Function Register during a read or write operation. It must be
cleared (logic 0) to access any other register.
1 = Enable access to the Divisor Latches of the Baud Generator and the AFR.
0 = Enable access to other registers (default).
6
Tx Break
R/W
Set Tx Break Enable
Ena 0 This bit is the Break Control bit. It causes a break condition to be transmitted to the
receiving UART. The Break Control bit acts only on SOUT and has no effect on the
transmitter logic.
1 = Serial output (SOUT) is forced to the Spacing State (break state, logic 0).
0 = The break transmission is disabled (default).
Note: This feature enables the CPU to alert a terminal in a computer communication
system. If the following sequence is followed, no erroneous or extraneous character
will be transmitted because of the break.
1. Load an all 0s, pad character, in response to THRE.
2. Set break after the next THRE.
3. Wait for the transmitter to be idle, (Transmitter Empty TEMT = 1), and clear break
when normal transmission has to be restored.
During the break, the transmitter can be used as a character timer to establish the
break duration.
During the break state, any word left in THR will be shifted out of the register but
blocked by SOUT as forced to break state. This word will be lost.
5
Forced
R/W
Tx and Rx Forced Parity Select
Parity Sel
0 When parity is enabled, this bit selects the forced parity format.
LCR[5] LCR[4] LCR[3]
Parity Select
1 1 1 Force parity to space = 0
1 0 1 Force parity to mark = 1
0 1 1 Even parity
0 0 1 Odd parity
X X 0 No parity
4
Even/Odd
R/W
Tx and Rx Even/Odd Parity Select
Parity Sel
0 This bit is only effective when LCR[3]=1. This bit selects even or odd parity format.
1 = Odd parity is transmitted or checked.
0 = Even parity is transmitted or checked (default).
3
Tx/Rx Parity
R/W
Tx and Rx Parity Enable
Ena 0 This bit enables parity generation.
1 = A parity is generated during the data transmission. The receiver checks for parity
error of the data received.
0 = No parity (default).
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