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PDF ( 数据手册 , 数据表 ) ISL1221

零件编号 ISL1221
描述 Real Time Clock/Calendar
制造商 Intersil Corporation
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ISL1221 数据手册, 描述, 功能
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ISL1221
®
Real Time Clock/Calendar with Event Detection and Frequency Output
Data Sheet
June 22, 2006
FN6316.0
Low Power RTC with Battery Backed
SRAM and Event Detection
The ISL1221 device is a low power real time clock with
Event Detect and Time Stamp function, timing and crystal
compensation, clock/calendar, power fail indicator, periodic
or polled alarm, intelligent battery backup switching with
separate FOUT output and 2 Bytes of battery-backed user
SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
VDD
RANGE
TEMP
RANGE
(°C)
PACKAGE
(Pb-Free)
ISL1221IUZ 1221Z
2.7V to 5.5V -40 to +85 10 Ld MSOP
ISL1221IUZ-T 1221Z
2.7V to 5.5V -40 to +85 10 Ld MSOP
Tape and Reel
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL1221
(10 LD MSOP)
TOP VIEW
X1 1
X2 2
VBAT 3
GND 4
EVIN 5
10 VDD
9 IRQ/EVDET
8 SCL
7 SDA
6 FOUT
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month, and Year
• Security and Event Functions
- Tamper detection with Time Stamp in Normal and
Battery Backed modes
- Event Detection During Battery Backed or Normal
Modes
- Selectable Event Input Sampling Rates Allows Low
Power Operation
- Selectable Glitch Filter on Event Input Monitor
• Separate FOUT pin with 15 Selectable Frequencies
• Single Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Automatic Backup to Battery or Super Cap
• Power Failure Detection
• On-Chip Oscillator Compensation
• 2 Bytes Battery-Backed User SRAM
• I2C Interface
- 400kHz Data Transfer Rate
• 400nA Battery Supply Current
• Small Package
- 10 Ld MSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• Set Top Box/Modem
• POS Equipment
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Test Meters/Fixtures
• Vending Machine Management
• Security and Anti Tampering Applications
- Panel/Enclosure Status
- Warranty Reporting
- Time Stamping Applications
- Patrol/Security Check (Fire or Light Equipment)
- Automotive Applications
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.







ISL1221 pdf, 数据表
www.DataSheet4U.com
ISL1221
X1
X2
FIGURE 10. RECOMMENDED CRYSTAL CONNECTION
VBAT
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event that the VDD
supply fails. This pin can be connected to a battery, a Super
Cap or tied to ground if not used.
EVIN (Event Input)
The EVIN pin is an input that is used to detect an externally
monitored event. When a high signal is present at the EVIN
pin, an “event” is detected. This input may be used for
various monitoring functions, such as the opening of a
detection switch on a chassis or door. The event detection
circuit can be user enabled or disabled (see EVEN bit) and
provides the option to be operational in battery backup
modes (see EVBATB bit). When the event detection is
disabled the EVIN pin is gated OFF. See functional
Description for more details.
FOUT (Frequency Output)
The FOUT pin outputs a clock signal which is related to the
crystal frequency. The frequency output is user selectable
and enabled via the I2C bus. It is an open drain active low
output. When not used, the output is high.
IRQ/EVDET (Alarm/Event Detect Output)
This dual function pin can be used as an interrupt alarm or
event detect output pin. Checking the status register will
show the type of interrupt, Alarm or Event Detect.
Interrupt Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that an alarm
has occurred and requests action. It is an open drain
active low output.
• The output will go low when an event is detected at the
EVIN pin. If the event detection function is enabled, the
IRQ/EVDET output will go low and stay low until the EVT
bit is cleared (see EVIN pin description).
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of
the device. The input buffer on this pin is always active (not
gated). It is disabled when the backup power supply on the
VBAT pin is activated to minimize power consumption.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It has an open drain output and may be ORed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor.
The output circuitry controls the fall time of the output signal
with the use of a slope controlled pull-down. The circuit is
designed for 400kHz I2C interface speeds. It is disabled
when the backup power supply on the VBAT pin is activated.
VDD, GND
Chip power supply and ground pins. The device will operate
with a power supply from VDD=2.7V to 5.5VDC. A 0.1µF
capacitor is recommended on the VDD pin to ground.
Functional Description
Power Control Operation
The power control circuit accepts a VDD and a VBAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
the ISL1221 for up to 10 years. Another option is to use a
Super Cap for applications where VDD is interrupted for up
to a month. See the Applications Section for more
information.
Normal Mode (VDD) to Battery Backup Mode
(VBAT)
To transition from the VDD to VBAT mode, both of the
following conditions must be met:
Condition 1:
VDD < VBAT - VBATHYS
where VBATHYS 50mV
Condition 2:
VDD < VTRIP
where VTRIP 2.2V
Battery Backup Mode (VBAT) to Normal Mode
(VDD)
The ISL1221 device will switch from the VBAT to VDD mode
when one of the following conditions occurs:
Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS 50mV
Condition 2:
VDD > VTRIP + VTRIPHYS
where VTRIPHYS 30mV
8 FN6316.0
June 22, 2006







ISL1221 equivalent, schematic
www.DataSheet4U.com
ISL1221
The effective series load capacitance is the combination of
CX1 and CX2:
CLOAD
=
----------------1------------------
-----1-----
CX1
+
C-----1X----2-⎠⎞
CLOAD
=
1---6--------b---5----+-----8-------b---4-----+----4-------b----3----+----2-2-------b---2----+----1--------b---1----+-----0---.-5--------b---0----+----9--⎠⎞
p
F
For example, CLOAD(ATR=00000) = 12.5pF,
CLOAD(ATR=100000) = 4.5pF, and CLOAD(ATR=011111) =
20.25pF. The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
BATTERY MODE ATR SELECTION (BMATR <1:0>)
Since the accuracy of the crystal oscillator is dependent on
the VDD/VBAT operation, the ISL1221 provides the capability
to adjust the capacitance between VDD and VBAT when the
device switches between power sources.
BMATR1
0
0
1
1
TABLE 12.
BMATR0
0
DELTA
CAPACITANCE
(CBAT TO CVDD)
0pF
1 -0.5pF (+2ppm)
0 +0.5pF (-2ppm)
1 +1pF (-4ppm)
DIGITAL TRIMMING REGISTER (DTR <2:0>)
The digital trimming bits DTR0, DTR1, and DTR2 adjust the
average number of counts per second and average the ppm
error to achieve better accuracy.
• DTR2 is a sign bit. DTR2 = “0” means frequency
compensation is >0. DTR2 = “1” means frequency
compensation is <0.
• DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm
adjustment and DTR0 gives 20ppm adjustment.
A range from -60ppm to +60ppm can be represented by
using these three bits (see Table 13).
TABLE 13. DIGITAL TRIMMING REGISTERS
DTR2
DTR REGISTER
DTR1
DTR0
ESTIMATED
FREQUENCY
PPM
0 0 0 0 (default)
001
+20
010
+40
011
+60
100
0
101
-20
TABLE 13. DIGITAL TRIMMING REGISTERS (Continued)
DTR2
DTR REGISTER
DTR1
DTR0
ESTIMATED
FREQUENCY
PPM
110
-40
111
-60
Alarm Registers
Addresses [0Ch to 11h]
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
Single Event Mode is enabled by setting the ALME bit to
“1”, the IM bit to “0”, and disabling the frequency output.
This mode permits a one-time match between the alarm
registers and the RTC registers. Once this match occurs,
the ALM bit is set to “1” and the IRQ output will be pulled
low and will remain low until the ALM bit is reset. This can
be done manually or by using the auto-reset feature.
Interrupt Mode is enabled by setting the ALME bit to “1”,
the IM bit to “1”, and disabling the frequency output. The
IRQ output will now be pulsed each time an alarm occurs.
This means that once the interrupt mode alarm is set, it
will continue to alarm for each occurring match of the
alarm and present time. This mode is convenient for
hourly or daily hardware interrupts in microcontroller
applications such as security cameras or utility meter
reading.
To clear an alarm, the ALM bit in the status register must be
set to “0” with a write. Note that if the ARST bit is set to 1
(address 07h, bit 7), the ALM bit will automatically be cleared
when the status register is read.
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1 – Alarm set with single interrupt (IM = ”0”)
A single alarm will occur on January 1 at 11:30am.
16 FN6316.0
June 22, 2006










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