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PDF ( 数据手册 , 数据表 ) WED2CG472512V-D2

零件编号 WED2CG472512V-D2
描述 DUAL KEY DIMM SRAM MODULE
制造商 White Electronic
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WED2CG472512V-D2 数据手册, 描述, 功能
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White Electronic Designs
WED2CG472512V-D2
ADVANCED*
16MB (4x512Kx72) SYNC / SYNC BURST,
DUAL KEY DIMM SRAM MODULE
FEATURES
DESCRIPTION
4x512Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Linear and Sequential Burst Support via MODE pin
Clock Controlled Registered Module Enable (EM#)
Clock Controlled Registered Bank Enables (E1#, E2#,
E3#, E4#)
Clock Controlled Byte Write Mode Enable (BWE#)
Clock Controlled Byte Write Enables (BW1# - BW8#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Asynchronous Output Enable (G#)
Internally Self-Timed Write
Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4)
Gold Lead Finish
3.3V ± 10% Operation
Frequency(s): 100, 83, 67, 50MHz
Access Speed(s): tKHQV = 7.5, 9, 10, 12, 15ns
Common Data I/O
High Capacitance (30pF) Drive, at Rated Access Speed
Single Total Array Clock
The WED2CG472512V is a Synchronous/Synchronous
Burst SRAM, 84 position Dual Key; Double High DIMM
(168 contacts) Module, organized as 4x512Kx72. The
Module contains sixteen (16) Synchronous Burst RAM
devices, packaged in the industry standard JEDEC
14mmx20mm TQFP placed on a Multilayer FR4 Substrate.
The Module Architecture is defined as a Sync/SyncBurst,
Flow-Through, with support for either linear or sequential
burst. This Module provides high performance, 2-1-1-1
accesses when used in Burst Mode, and when used in
Synchronous Only Mode, provides a high performance
cost advantage over BiCMOS asynchronous device
architectures.
Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP#/ADV# High, which provides for
Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in
relation to an externally supplied clock, Registered
Address, Registered Global Write, Registered Enables as
well as an Asynchronous Output Enable. This Module has
been defined with full flexibility, which allows individual
control of each of the eight bytes, as well as Quad Words
in both Read and Write Operations.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Aug. 2002
Rev. B
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com







WED2CG472512V-D2 pdf, 数据表
White Electronic Designs WED2CG472512V-D2
ADVANCED
FIG. 5
CK
Ex#
ADDR
GW#
G#
SYNC (NON-BURST) WRITE CYCLE
tKHKH
tKHKL tKLKH
tAVKH
tKHAX
Addr 1
tDVKH
Write Cycle
Addr 1
tGWLKH
Addr 2
tKHGWH
tKHGH
tKHDX
tGHKH
Back to Back Writes
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Aug. 2002
Rev. B
8 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com














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