DataSheet8.cn


PDF ( 数据手册 , 数据表 ) ADF7021

零件编号 ADF7021
描述 High Performance Narrow-Band Transceiver IC
制造商 Analog Devices
LOGO Analog Devices LOGO 


1 Page

No Preview Available !

ADF7021 数据手册, 描述, 功能
Data Sheet
High Performance
Narrow-Band Transceiver IC
ADF7021
FEATURES
Low power, narrow-band transceiver
Frequency bands using dual VCO
80 MHz to 650 MHz
862 MHz to 950 MHz
Modulation schemes
2FSK, 3FSK, 4FSK, MSK
Spectral shaping
Gaussian and raised cosine filtering
Data rates supported
0.05 kbps to 32.8 kbps
2.3 V to 3.6 V power supply
Programmable output power
−16 dBm to +13 dBm in 63 steps
Automatic PA ramp control
Receiver sensitivity
−130 dBm at 100 bps, 2FSK
−122 dBm at 1 kbps, 2FSK
−113 dBm at 25 kbps, raised cosine 2FSK
Patent pending, on-chip image rejection calibration
On-chip VCO and fractional-N PLL
On-chip, 7-bit ADC and temperature sensor
Fully automatic frequency control loop (AFC)
Digital received signal strength indication (RSSI)
Integrated Tx/Rx switch
0.1 μA leakage current in power-down mode
APPLICATIONS
Narrow-band standards
ETSI EN 300 220, FCC Part 15, FCC Part 90, FCC Part 95,
ARIB STD-T67
Low cost, wireless data transfer
Remote control/security systems
Wireless metering
Private mobile radio
Wireless medical telemetry service (WMTS)
Keyless entry
Home automation
Process and building control
Pagers
RLNA
RSET
FUNCTIONAL BLOCK DIAGRAM
CE CREG(1:4)
TEMP
SENSOR
MUX
7-BIT ADC
LDO(1:4)
MUXOUT
TEST MUX
RFIN
RFINB
LNA
IF FILTER
RSSI/
LOG AMP
2FSK
3FSK
4FSK
DEMODULATOR
CLOCK
AND DATA
RECOVERY
Tx/Rx
CONTROL
GAIN
PA RAMP
AGC
CONTROL
AFC
CONTROL
SERIAL
PORT
RFOUT
÷1/÷2
VCO1
÷2
DIV P
N/N + 1
Σ-
MODULATOR
VCO2
MUX
CP PFD
DIV R
OSC
2FSK
3FSK
4FSK
MOD CONTROL
CLK
DIV
GAUSSIAN/
RAISED COSINE
FILTER
3FSK
ENCODING
TxRxCLK
TxRxDATA
SWD
SLE
SDATA
SREAD
SCLK
L1 L2 VCOIN CPOUT
OSC1 OSC2
Figure 1.
CLKOUT
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







ADF7021 pdf, 数据表
ADF7021
RECEIVER SPECIFICATIONS
Table 3.
Parameter
SENSITIVITY
Min Typ
2FSK
Sensitivity at 0.1 kbps
Sensitivity at 0.25 kbps
Sensitivity at 1 kbps
Sensitivity at 9.6 kbps
Sensitivity at 25 kbps
Gaussian 2FSK
Sensitivity at 0.1 kbps
Sensitivity at 0.25 kbps
Sensitivity at 1 kbps
Sensitivity at 9.6 kbps
Sensitivity at 25 kbps
GMSK
Sensitivity at 9.6 kbps
Raised Cosine 2FSK
Sensitivity at 0.25 kbps
Sensitivity at 1 kbps
Sensitivity at 9.6 kbps
Sensitivity at 25 kbps
3FSK
Sensitivity at 9.6 kbps
−130
−127
−122
−115
−110
−129
−127
−121
−114
−111
−113
−127
−121
−114
−113
−110
Raised Cosine 3FSK
Sensitivity at 9.6 kbps
−110
Sensitivity at 19.6 kbps
−106
4FSK
Sensitivity at 9.6 kbps
Sensitivity at 19.6 kbps
Raised Cosine 4FSK
Sensitivity at 9.6 kbps
−112
−107
−109
Sensitivity at 19.2 kbps
−103
Sensitivity at 32.8 kbps
−100
INPUT IP3
Low Gain Enhanced Linearity
Mode
Medium Gain Mode
High Sensitivity Mode
−3
−13.5
−24
Max
Data Sheet
Unit Test Conditions/Comments
Bit error rate (BER) = 10−3, low noise amplifier (LNA) and
power amplifier (PA) matched separately
dBm
dBm
dBm
dBm
dBm
fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
fDEV = 4 kHz, high sensitivity mode, IF_BW = 18.75 kHz
fDEV = 10 kHz, high sensitivity mode, IF_BW = 25 kHz
dBm
dBm
dBm
dBm
dBm
fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
fDEV = 4 kHz, high sensitivity mode, IF_BW = 18.75 kHz
fDEV = 10 kHz, high sensitivity mode, IF_BW = 25 kHz
dBm fDEV = 2.4 kHz, high sensitivity mode, IF_BW = 18.75 kHz
dBm
dBm
dBm
dBm
fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
fDEV = 1 kHz, high sensitivity mode, IF_BW = 12.5 kHz
fDEV = 4 kHz, high sensitivity mode, IF_BW = 18.75 kHz
fDEV = 10 kHz, high sensitivity mode, IF_BW = 25 kHz
dBm fDEV = 2.4 kHz, high sensitivity mode, IF_BW = 18.75 kHz,
Viterbi detection on
dBm fDEV = 2.4 kHz, high sensitivity mode, IF_BW = 12.5 kHz,
alpha = 0.5, Viterbi detection on
dBm fDEV = 4.8 kHz, high sensitivity mode, IF_BW = 18.75 kHz,
alpha = 0.5, Viterbi detection on
dBm fDEV (inner) = 1.2 kHz, high sensitivity mode, IF_BW = 12.5 kHz
dBm fDEV (inner) = 2.4 kHz, high sensitivity mode, IF_BW = 25 kHz
dBm
dBm
dBm
dBm
fDEV (inner) = 1.2 kHz, high sensitivity mode,
IF_BW = 12.5 kHz, alpha = 0.5
fDEV (inner) = 1.2 kHz, high sensitivity mode,
IF_BW = 18.75 kHz, alpha = 0.5
fDEV (inner) = 1.8 kHz, high sensitivity mode, IF_BW = 25 kHz,
alpha = 0.7
Two-tone test, fLO = 860 MHz, F1 = fLO + 100 kHz, F2 = fLO − 800 kHz
LNA_GAIN = 3, MIXER_LINEARITY = 1
dBm LNA_GAIN = 10, MIXER_LINEARITY = 0
dBm LNA_GAIN = 30, MIXER_LINEARITY = 0
Rev. D | Page 8 of 62







ADF7021 equivalent, schematic
ADF7021
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
VCOIN 1
CREG1 2
VDD1 3
RFOUT 4
RFGND 5
RFIN 6
RFINB 7
RLNA 8
VDD4 9
RSET 10
CREG4 11
GND4 12
ADF7021
TOP VIEW
(Not to Scale)
36 CLKOUT
35 TxRxCLK
34 TxRxDATA
33 SWD
32 VDD2
31 CREG2
30 ADCIN
29 GND2
28 SCLK
27 SREAD
26 SDATA
25 SLE
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
Figure 10. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic
Description
1 VCOIN Regulator Voltage for PA Block and VCO Cores. The tuning voltage on this pin determines the output
frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher the output
frequency.
2 CREG1 Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and
ground for regulator stability and noise rejection.
3 VDD1
Voltage Supply for PA Block and VCO Cores. Place decoupling capacitors of 0.1 μF and 100 pF as close as
possible to this pin. Tie all VDD pins together.
4 RFOUT The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. Impedance
match the output to the desired load using suitable components (see the Transmitter section).
5 RFGND Ground for Output Stage of Transmitter. Tie all GND pins together.
6 RFIN
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer (see the LNA/PA Matching section).
7 RFINB
Complementary LNA Input (see the LNA/PA Matching section).
8 RLNA
9 VDD4
External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
Voltage Supply for LNA/MIXER Block. Decouple this pin to ground with a 10 nF capacitor.
10 RSET
External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with 5% tolerance.
11 CREG4
Regulator Voltage for LNA/MIXER Block. Place a 100 nF capacitor between this pin and GND for regulator
stability and noise rejection.
12, 19, 22 GND4
Ground for LNA/MIXER Block.
13 to 18 MIX_I, MIX_I, Signal Chain Test Pins. These pins are high impedance under normal conditions; leave the pins unconnected.
MIX_Q, MIX_Q,
FILT_I, FILT_I
20, 21, 23 FILT_Q, FILT_Q, Signal Chain Test Pins. These pins are high impedance under normal conditions; leave the pins unconnected.
TEST_A
24 CE
Chip Enable. Bringing CE low puts the ADF7021 into complete power-down. Register values are lost when CE
is low, and the device must be reprogrammed once CE is brought high.
25 SLE
Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of the
four latches. A latch is selected using the control bits.
26 SDATA
Serial Data Input. The serial data is loaded MSB first with the 4 LSBs as the control bits. This pin is a high
impedance CMOS input.
27 SREAD
Serial Data Output. This pin is used to feed readback data from the ADF7021 to the microcontroller. The SCLK
input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.
28 SCLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 32-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
Rev. D | Page 16 of 62










页数 30 页
下载[ ADF7021.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
ADF7020High Performance ISM Band FSK/ASK Transceiver ICAnalog Devices
Analog Devices
ADF7020-1High Performance FSK/ASK Transceiver ICAnalog Devices
Analog Devices
ADF7021High Performance Narrow-Band Transceiver ICAnalog Devices
Analog Devices
ADF7021-NHigh Performance Narrow-Band Transceiver ICAnalog Devices
Analog Devices

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap